Memory characterization and prediction of application processor performance and power consumption

As the speed gap between ultra-fast CPU cores and relatively slow memories continues to grow, memory systems may become the main bottleneck restricting system performance today. In addition, low power consumption is another important design consideration, especially with the increasing number of battery-powered devices. Low power consumption means longer battery life and device usage time. In common applications, memory power consumption usually accounts for a considerable part of the application processor power consumption, and as memory designs become more complex, larger in capacity, and more layered, memory power consumption tends to increase rapidly. Therefore, reducing memory power consumption is very beneficial to extending battery life. In order to better understand the inherent behavior of various applications, it is necessary to explore the characteristics of memory and establish memory models to determine whether the application involves frequent memory access operations and even help predict the performance of the application.

This paper provides a simple and economical method to dynamically characterize the computation and memory composition of an application with acceptable accuracy.

Methods for describing memory characteristics

If no memory operations are involved, then CPU utilization should scale linearly with the CPU core frequency, and the application cost (defined as the product of CPU utilization and CPU frequency) should remain constant. However, after taking memory accesses into account, CPU utilization is no longer linear with core frequency. At higher frequencies, memory tends to have a greater impact on performance because the CPU has to spend more CPU cycles waiting for memory responses (here we assume that memory frequency does not vary with CPU frequency). In this sense, applications can be divided into two types: compute-bound and memory-bound.

Next, we will describe how to characterize memory characteristics using three different methods and help determine the CPU utilization of the application. Here, hardware performance information is collected by looking at the Performance Monitoring Unit (PMU). Therefore, Marvell's method only works on systems with PMU hardware support.

1. Overall data cache miss rate: Intuitively, a higher data cache miss rate means more memory traffic. To obtain the data cache miss rate, we need to monitor the total number of access operations and misses of the L1 data cache and L2 data cache (if any).

2. Main memory access rate: The occupancy rate of the external memory controller directly indicates the utilization rate of the memory. In order to obtain the main memory access rate value, two types of PMU information must be collected: the total number of cycles occupied by the memory controller; the total number of cycles in the monitoring window.

3. Data stall rate: Pipeline stalls are mainly caused by data dependencies, and the reason why data is unavailable is that the memory access speed is much lower than the CPU speed. Therefore, the number of pipeline stalls reflects the memory traffic. In addition, the number of pipeline stalls also indicates the importance of memory access. Not every memory access has a critical impact on the final performance, so it is quite useful to keep track of memory access operations that affect performance due to data dependencies. Using this method, you can monitor the events caused by data dependencies. In addition, the total number of cycles must be recorded to calculate the data stall rate in each window.