Engineers’ technical sharing: Why should digital power supply pay attention to accuracy?

An example of an error budget

Let's use an actual IC specification and consider how accuracy comes into play. Let's use a high-end FPGA. The FPGA's parameter table (below) determines the supply voltage at which the IC is guaranteed to operate properly. If the supply voltage is outside this range, the device is not guaranteed to operate properly.

Figure 1: FPGA Specifications Let’s focus on the VCC rail , which has a ±30mV fluctuation around its nominal value of 0.85V. For a 0.85V rail, the error is ±3.5%.

At first glance, one would think that a ±3% POL would take care of this. Unfortunately, there are other considerations.

Figure 2: 10A POL load response

This scope screenshot shows a 10A load pulse at the output of the VCC POL. There is about 8mV of ripple and a brief 20mV drop. This raises the question: Do these artifacts have to be within the ±3.3% specification? The waveform in this scope picture appears at the output of the POL. We must ask: What is the load experiencing?

Figure 3: Power distribution network (PDN) schematic

This PDN schematic from the DesignCon 2006 “Comparison of Power Distribution Network Design Methods” shows filtering in the package and on the chip. The PDN, package decoupling, and on-chip capacitors can filter out some of the high-frequency portion of transients. So the answer to the transient margin question is: it depends. Generally, only the package side of the PDN will filter out the highest frequencies. Ripple is another matter. Ripple is lower frequency, and the chip will see the same ripple as it sees at the load pins. So, for the purposes of our analysis, we will assume that the ripple consumes some of the error margin and ignore transients.

With 8mV ripple, we only have ±22mV left in our error budget, which translates to about ±2.5% accuracy. Unfortunately, we are not done yet. We must consider overvoltage (OV) and undervoltage (UV) monitors. If you look back at one of my previous articles, “Digital Power Monitoring and Telemetry,” the OV/UV monitors are comparators with DACs that set the trip points. What we are concerned about is undervoltage and overvoltage accuracy.

The accuracy of the monitors is part of the error budget, as we want to set the UV monitors above specification and the OV monitors below specification. This is the only way to guarantee that the power rails meet the IC power supply specifications. (Note: While we can usually add some filtering to the monitors so that transients don't trip them, ripple will always cause them to trip.)

Now, let's use the accuracy of the LTC3880 supervisor , which is ±2%. On our 0.85V rail, that's 17mV. Now, we only have 4mV of headroom left! The POL output voltage accuracy must now be 0.5%! Is this achievable?

The LTC3880 datasheet shows that the output accuracy of the supervisor is ±0.5%. Our power rail meets the specification, and the supervisor ensures that it is working properly. In the previous article, we talked about that if the specification is not met, it will selectively trigger and shut down and send a fault to the basic board management controller (BMC).

Is there a compromise?

It depends on the quality level you want. If you remove the monitor from the specification and rely on the control loop, the required control loop accuracy is 2%, and the LTC3880 improves by a factor of 4. This means that it can even support supply rails below 0.85V . However, there is one last aspect that we have not considered. Just when you think we are done, there is actually more to deal with.

What about margin adjustment?

In a production environment, power systems are run at (or above) high and low specifications to eliminate any marginality in the system. In our design scenario, this means running the system at ±3.5% accuracy. During margining, the monitor will “give way” a bit, as the goal here is to ensure system reliability across the full specification range.

We need to ensure that the power rails can work properly under extreme conditions, so we need to use control loop accuracy to enable the power rail settings to exceed the extreme conditions to ensure that the extreme conditions even exceed the actual values ​​of the extreme conditions. If the control loop accuracy is 0.5%, then we should set the power rails to ±4%. What if the control loop accuracy is only 2% (similar to the supervisor)? The value should be ±5.5%.

No big deal, right?

Margin testing has the potential to trigger expensive failures if the FPGA application loses timing margin due to higher margin values. You may need to add timing margin to the design to pass margin testing, and if you can’t allow for the increased margin, you may lose yield. Or you can reduce the margin value and compromise quality (let some defects slip). Either way, it’s either you or your customers who lose. If you do the right thing and set the margin values ​​correctly, you will slow down the project, and you will lose yield and hurt your bottom line. And if you cheat on margin testing, your customers will lose because their systems won’t be reliable. So control loop accuracy really matters. It’s a big deal.

Summarize

We studied the FPGA specifications and performed an error budget. We found other error budget components including: ripple, control loop accuracy, monitor accuracy, and margin accuracy. Directly comparing the FPGA specifications to the performance metrics of the POL does not tell the whole story. The accuracy of the POL must be much higher than the specifications given in the FPGA data sheet to ensure that the device operates within the specification range and to ensure reliability of both within the entire specification range while maintaining high yield in production.