Design of transformer-coupled front end for high performance analog-to-digital converters

The design of systems using high-speed analog-to- digital converters (ADCs) with high input frequencies (IFs) has always proven to be a challenging task. The use of transformers makes this task even more difficult because transformers have inherent nonlinearities that can make performance substandard. This article categorizes the issues that should be considered when designing high-speed sub-ranging ADCs using transformer- coupled front ends .

Design parameters

There are several important parameters to consider when designing the front end.

The input impedance is the characteristic impedance of the design. In most cases it is 50 Ω, but some designs require other impedance values. Transformers are essentially transimpedance devices because they can couple circuits of different characteristic impedances when necessary so that the total system load is well balanced.

Bandwidth refers to the range of frequencies used by the system. This bandwidth can be narrow or wide, distributed over baseband (first Nyquist frequency), or covering multiple Nyquist zones.

Input drive level is a function of the bandwidth parameter and sets the system gain required for a particular application. Drive level is highly dependent on the front-end components used, such as filters and transformers, and this requirement can make this parameter one of the most difficult to achieve.

The voltage standing wave ratio (VSWR) measures the amount of power reflected into the load over the bandwidth of interest. This parameter sets the input drive level required to achieve full-scale input to the ADC.

Passband flatness is the amount of fluctuation in performance within a specified bandwidth. This can be due to ripple effects or a very slow roll-off characteristic of a simple low-pass filter. Passband flatness is often less than or equal to 1dB and is critical to the overall system setup.

The signal-to-noise ratio (SNR) is the relationship between the signal seen by the converter and its own noise. In the front end, the SNR can be degraded due to bandwidth, signal quality (jitter), and gain. Note that when the signal is amplified, the noise component is also amplified.

Spurious Free Dynamic Range (SFDR) is the ratio of the full-scale rms value to the rms value of the peak spurious spectral components. This is mainly caused by two characteristics of the front end. The first characteristic is the linearity of the transformer, or the balance quality, which is related to the second harmonic distortion; the second characteristic is the matching relationship between the gain and the input. As the required gain increases, matching becomes more and more difficult, and the parasitic components of the nonlinear transformer (usually regarded as a third harmonic) will increase.

Transformer parameters

A transformer can be simply viewed as a bandpass filter.

Insertion loss, which represents the amount of loss in a transformer at a specific frequency, is the most common measurement parameter in a transformer data sheet, but it should not be the only consideration in a design.

Return loss is the transformer seen by the primary side when the secondary of the transformer is terminated. For example, an ideal 1:2 impedance transformer with 100 Ω impedance at the secondary will see 50 Ω impedance reflected at the primary. However, this is not always true, as the impedance reflected by the primary will change with frequency. As the impedance ratio increases, the return loss will also change accordingly.

Amplitude and phase imbalance is a key performance characteristic of transformers. When the design requires an IF frequency above 100MHz, these two specifications can give the designer an idea of ​​how much nonlinearity to expect. As the frequency increases, the transformer's nonlinearity increases. Phase imbalance is often the dominant imbalance, resulting in even-order distortion or the addition of second harmonics.

ADC parameters

ADCs can be divided into two types: buffered and unbuffered. Unbuffered ADCs tend to consume much more power than buffered ADCs, but buffered ADCs are easier to drive.

The switched capacitor ADC is a specific example of an unbuffered ADC. The front-end design is directly connected to the sample-and-hold (SAH) network inside the ADC. This brings two problems: one is that the input impedance of the ADC changes over time and in different modes; the second is charge injection, which is reflected on the analog input of the ADC, which brings filter settling problems.

带有缓冲的ADC的理解和使用最为方便。通过采用能够抑制电荷注入带来的尖峰的隔离缓冲器，可以显著降低开关的瞬态。与开关电容ADC中的情形不同，输入的端接特性在整个规定的ADC带宽上不会随着模拟输入频率的不同而发生变化，恰当的驱动电路的选择将变得更为方便。带缓冲的输入级的不利之处，就在于会使得 ADC消耗更多的功率。设计示例

Design examples for baseband and IF applications are shown in Figures 1 and 2, respectively.

In baseband applications, the input impedance of the ADC is generally high, so input matching is less important and easier to achieve. Often one or two small series resistors to attenuate charge injection effects plus simple differential input capacitors are sufficient. In this way, only a simple filter is needed to attenuate broadband noise for optimal performance.

High frequency applications require the designer to think a little more. To optimize the input match, the input impedance needs to be made as resistive as possible by matching the front-end trace mode impedance. The "capacitive" term can be eliminated by using a series or parallel inductor or ferrite bead (the former is shown in the figure).

In summary, matching the input gives good bandwidth, gain flatness (less variation in power drive), and better performance.

Baseband applications with a buffered ADC also use a simple network similar to the switched capacitor ADC configuration. Note that the secondary side should be terminated to match the input of the primary side.

In Figure 2, a double balun (balanced/unbalanced conversion) is used for high IF applications. This allows the input to be well balanced up to 300MHz, keeping second-order distortion to a minimum.

summary

There are many parameters that must be considered in the design to achieve the best performance. Transformers vary widely. Designers who understand the specific transformer performance parameters and consult the manufacturer for parameters that are not given can better predict the characteristics of their design. High-IF designs are sensitive to transformer phase imbalance, so these designs may require two transformers or a balun.

It is also important to know whether the ADC being used is buffered or unbuffered. The input impedance of an unbuffered ADC varies over time, making the design more difficult at high IFs. To optimize the design, the inputs should be tracked and matched. Use ferrite beads or low-Q inductors to eliminate the input capacitance component of a switched capacitor ADC. This maximizes input bandwidth, allows for better input matching, and maintains SFDR performance. Buffered ADCs are easier to design, even at high IFs, but they consume more power. Regardless of the ADC type used, baseband applications have the easiest design effort.