Design Methods for Connecting Motor Drivers to PWM Sources

Connecting a PWM logic signal source to a battery-powered motor drive is a challenge. This article describes a design method for connecting a motor driver to a PWM source, including relevant equations and component selection guidelines. The circuit used in this method includes examples with accuracy and sensitivity analysis.

Connecting the Motor Driver to the PWM Source

The LM4570 is an eccentric rotating mass (ERM) and linear resonant excitation (LRA) motor driver IC for mobile phones and other portable media devices. This design details the process of connecting the LM4570 to a PWM source.

While LRA motors are driven by an AC bipolar waveform at close to the resonant frequency of the LRA, ERM motors are driven primarily by DC voltage. Since DC power is required, there may not be an AC coupling capacitor in series with the input of the driver IC.

Designing a PWM interface to a driver IC requires considerable mathematical knowledge to ensure correct operation.

The first step in designing this circuit is to determine the required gain. The PWM source can provide the following voltage levels:

Formula 1:

Where VIN(PEAK) is the single-ended peak output voltage that the PWM source can provide, and VLOGIC is the PWM logic high voltage. If the PWM source can achieve 0% and 100% duty cycle, use Equation 1. If the PWM source cannot achieve 0% and 100% duty cycle, use Equation 1a because VIN(PEAK) needs to be reduced accordingly according to this equation:

Formula 1a:

Where DC(MAX) and DC(MIN) are the maximum and minimum duty cycles of the PWM source, respectively. Please select DC(MAX) or DC(MIN) to generate the minimum VIN(PEAK) term to ensure a symmetrical swing.

The next step is to determine the peak output voltage VOUT(PEAK) required to flow through the ERM motor. This value can be set to 3V or lower for consistent operation at all battery voltages, or to 4.2V for maximum overdrive when the battery is fully charged. The peak output voltage must be verified against the ERM motor specifications to ensure that its amplitude and duration do not exceed the specifications specified by the ERM motor manufacturer. Using VOUT(PEAK) and VIN(PEAK), we can calculate the system gain:

Equation 2:

Where "Gain" is the gain required from the single-ended PWM source to the output of the bridge-tied load (BTL) amplifier.

Analysis of the required gain for the circuit in Figure 1 shows that a 2X gain correction is required at the BTL output. The resistor can be calculated using the following equation:

Formula 3:

The easiest way is to choose RF as 200k and then calculate the sum of RG1 and RG2. Splitting RG into two resistors allows the addition of a bypass capacitor CF to form a first-order low-pass filter. This low-pass filter prevents the high-frequency content from the PWM signal from being radiated by the amplifier and the ERM motor. By choosing RG1 and RG2 to be essentially the same value, their sum can be used and the required gain can be calculated using Equation 3. The cutoff frequency of the low-pass filter can be calculated using the following equation:

Formula 4:

Where f-3dB is the cutoff frequency of the low pass filter, usually set at 2kHz to 5kHz.

The final step in designing this circuit is to properly bias REF2 (see Figure 1). This is necessary because the average DC level of the PWM source (one-half VLOGIC) is different from the average DC level at the output (one-half the change in VBATTERY). This is accomplished by selecting resistors R1 and R2 in Figure 1. Note that the Thevenin impedance of the REF1 pin is approximately 10k, so we will choose R2 to be approximately 200k to make the loading effect negligible. The bias voltage is calculated as follows:

Formula 5:

Figure 1: LM4570 motor driver with PWM interface

Where R1 is the impedance equivalent to R1A and R1B in parallel (forming the voltage divider of these two resistors). Similarly, assuming that the duty cycle of the PWM input is 50% and the output is balanced with VDD/2, the voltage calculation formula at the IN terminal can be obtained:

Formula 6:

Obviously, Equation 5 and Equation 6 are actually the same in form, so we can see that we only need to make R2 equal to RF and make R1A and R1B twice the value of RG. One benefit of using a symmetrical circuit is that the VDD term is removed from the calculation, making the circuit insensitive to changes in battery voltage.

To test these calculations, we will use an example with the following parameters: VLOGIC = 1.5V, VOUT(PEAK) = 3.0V

To achieve the above values, we need a "gain" of 4. Selecting RF as 200k and using Equation 3, we can calculate RG equals 100k, or RG1 and RG2 equal to 49.9k. Since the two parts are symmetrical, selecting R2 as 200k and using Equation 3 again, we can calculate R1 equals 100k, or R1A and R1B equal to 200k. To evaluate the performance of this circuit, we performed a parameter sweep from 0% to 100% input duty cycle while increasing the battery voltage from 3.0V to 3.6V to 4.2V. In addition, we used Monte Carlo analysis to detect the resistor values ​​to determine their sensitivity (the results are shown in Figure 2).

Figure 2: Simulation results

As shown in Figure 2, the two outputs VO1 and VO2 are complementary to each other. Note that the two signals always cross at zero at the 50% duty cycle point, or 0.75V on the input. They also cross at half the battery voltage, even when the battery voltage varies across its usable range.

The simulation in Figure 2 is also a Monte Carlo scan with a resistor tolerance of 1%. As shown in the figure, each trace is slightly wider, which represents only a negligible impact on performance.

As shown in Figure 2, the two outputs VO1 and VO2 are complementary to each other. Note that the two signals always cross at zero at the 50% duty cycle point, or 0.75V on the input. They also cross at half the battery voltage, even when the battery voltage varies across its usable range.

The simulation in Figure 2 is also a Monte Carlo scan with a resistor tolerance of 1%. As shown in the figure, each trace is slightly wider, which represents only a negligible impact on performance.