Portable Power Analyzer Design - Hardware Design (Part 2)

3.3 System Hardware Design

The hardware design of the power analyzer adopts a two-stage design, namely the host and the probe. The probe part design includes microwave module, frequency division module and power detection module (the frequency division module will be introduced in the frequency measurement design part). The host part mainly includes: power supply, data acquisition module, FPGA and ARM control part, and external input devices such as LCD display and keyboard are also included.

3.3.1 Probe design

3.3.1.1 Microwave Module

The microwave module includes one input at the front end, an attenuator, a power divider, two outputs at the back end, and a module control signal input. The RF pulse signal is injected into the system through the RF coaxial connector. The RF coaxial connector uses SMA threaded connection with an impedance of 50 ohms, which matches the system impedance. The two back-end outputs are processed by the microwave module, including power output and frequency output. The module control signal is mainly the power control, signal channel switching, and attenuation switching of the microwave module.

The control signals of the microwave module mainly include three categories: power control, switch control, and attenuation control. The power supply realizes the connection between the internal and external power supplies. It mainly includes three parts: +5v, -5v and ground. FPGA controls the selection switch inside the microwave module through the switch control signal, switching frequency and power. The power divider inside the microwave module is used to divide the signal into two signals with the same phase and equal amplitude, and send them to the power output end and the frequency output end. The attenuation network design of the microwave module will be introduced in detail in the next section of the attenuation circuit. The hardware block diagram of the microwave module is shown in Figure 3-3.

3.3.1.2 Attenuation circuit

In order to expand the power measurement range and measurement precision, the attenuation measurement method is used. Power attenuation refers to the attenuation of the signal before demodulation, which can expand the detection range of the detector and improve the detection accuracy. Back-end attenuation is the attenuation control of the signal after demodulation, which is mainly used to increase the range of A/D conversion.

Power attenuation is controlled by the attenuation network inside the microwave module. The power attenuation network consists of two parts: a precision attenuator and a digital control. The attenuator part consists of a π-type network composed of N groups of precision resistors. According to the principle of impedance matching, it is switched by micro relays to form an attenuator with a total attenuation of NdB and a change step of N dB. The basic working principle of the Pi-type attenuator is shown in Figure 3-4 below:

L1 is a straight-through path, directly connecting two single-pole switches, and L2 is connected to a π-type fixed attenuation resistor network. Assume that the transmission attenuation of L1 is IL1, and the transmission attenuation of L2 is IL2 + X dB, where X dB is the attenuation of the π-type attenuation network. The attenuation of each bit A tt can be expressed by formula (1):

The fixed attenuator using silicon thin film resistor technology is directly mounted on the cavity. The attenuator is small in size, highly stable, can withstand high power, and can still maintain a flat attenuation characteristic in the RF band. The switch is composed of PIN diodes that work in two stable states of conduction and cutoff, and is less affected by temperature; the attenuation resistor has good temperature stability; the Π-type network itself has self-temperature compensation, so the attenuator can maintain almost constant attenuation in the temperature range of -55 to 85°C, and the switch-fixed attenuator structure can maintain good matching.

According to the optimal working range of the detection circuit and the power measurement range of the power detection chip, in the power measurement, the attenuation control of 0 and 20dBm is selected for the attenuation network of the microwave attenuation network. The attenuation control end of the attenuation network inside the microwave module is connected to the FPGA. The ARM generates a control signal through the FPGA and sends it to the power attenuator to achieve 0dB or 20dB attenuation of the input power signal.

3.3.3 RF Envelope Detection Module

In this design, the input impedance of the logarithmic detector chip is 50. When the device under test is not a standard signal generating device, in order to ensure impedance matching and the signal can be accurately injected into the input end of the subsequent RF detector chip, the power attenuation network designed at the front end provides power attenuation while providing input and output impedances that match the system characteristic impedance. By adjusting the resistance value of the grounded shunt resistor, the attenuated output impedance is ensured to be 50, thereby matching the input impedance of the logarithmic detector chip.

3.3.3.1 Peak detection circuit

The detector is one of the conventional components in RF technology and is a key component in RF signal detection, automatic gain control, power detection, and amplitude stabilization. In many cases, the detector is required to have good standing wave characteristics, power flatness, and high sensitivity in a wide frequency band.

AD8318 is a semiconductor-based monolithic detector that is superior to traditional products. It has a higher cost-performance ratio than module solutions and higher accuracy than discrete diode-based detectors. It uses ADI's XFCB-3SiGe production technology to provide faster speed, accuracy and temperature stability. AD8318 has a unique combination of high precision and wide dynamic range, making it suitable for many types of wireless communication infrastructure equipment, including GSM, CDMA and W-CDMA cellular base stations, WLAN802.11 applications and point-to-point fixed wireless systems, for received signal strength indication and transmission power level detection. The basic characteristics of AD8318 are as follows:

(1) Wide frequency band: can accurately measure the power of RF signals within the bandwidth of 1MHz~8GHz;

(2) Large dynamic range and high accuracy: At 5 GHz, the dynamic range exceeds 55 dB and the accuracy is better than +1 dB; at 8 GHz, the dynamic range exceeds 58 dB and the accuracy is better than +3 dB;

(3) Good stability: The temperature drift can be adjusted to the required frequency band, and the stability from -40℃ to 85℃ is better than +0.5dB, which can fully meet the specified technical indicators;

(4) Use voltage to indicate the size of input information;

(5) Low noise, input power noise 1.15nV/√Hz;

(6) +5V single voltage power supply, the maximum current is only 68mA, and the minimum power consumption is only 1.5mW;

(7) An on-chip temperature sensor is integrated, which can provide a 2mV/℃ output voltage for additional temperature compensation and system monitoring;

(8) Provides the fastest output response of 8ns, suitable for burst RF pulse detection;

(9) It adopts a small-size 4mm*4mm, 16-pin pin-frame chip-scale package.

The internal structure of AD8318 determines its excellent performance. In addition to the dual square unit mentioned above,

As shown in Figure 3-5. It has a cascade amplifier chain consisting of 9 amplifier units. Each amplifier unit can achieve a voltage gain of 8.7dB, which realizes the logarithmic function of AD8318. Due to the precise bias design, the gain is still very stable when the temperature exceeds the rated value and the input signal changes beyond the rated range. The signal is input from the INHI terminal and passes through the cascade amplifier unit. Since the gain of each amplifier unit is DC coupled, the signal is amplified step by step when passing through each amplifier unit, so the final gain is very large. At each gain output terminal, there is a detector with a square effect to shape the signal, and there is a compensation feedback circuit inside the AD8318 to compensate the signal. Through a series of measures, the output signal is very accurate. Therefore, the RF signal voltage input from INHI is converted into a differential current signal that changes with the input signal amplitude after amplification. The mean value of this differential current signal varies with the input RF level. After the current waveform is shaped and filtered, it is converted into a voltage output through current voltage conversion. In this way, the input signal power is converted into a change in the output voltage value. We only need to follow the corresponding formula between the output voltage amplitude and the input signal power to calculate the power value of the measured signal at the current moment.

The output voltage amplitude and input signal power have the following linear logarithmic relationship:

Among them, X is the feedback factor in the formula VSET = VOUT /X, which can be adjusted to 1 or 2 in the circuit (by changing the resistance between the VOUT and VSET pins and the resistance between the VSET pin and the ground); VSLOPE /DEC is -500mV/decade; VSLOPE /dB is approximately -25mV/dB, and VINTERCEPT is the logarithmic linear part of the input-output relationship curve intercepted by X. For a sinusoidal input signal, VINTERCEPT is +7dBV. At the same time, the AD8318 chip adds a 0.5V offset voltage (VOFFSET) to the detection signal, so the minimum value of the output signal is X* VOFFSET. That is to say, when X=1, the minimum value of VOUT is 0.5V. AD8318 has control mode and measurement mode to choose from. Different modes can be selected according to different connections of the OUT V pin. We choose the measurement mode of AD8318. Figure 3-7 shows the connection diagram of AD8318:

At this time, the slope of the input-output relationship curve of AD8318 is -50mV/dB, and the amplitude range of the detection output signal is 0.5V~2.5V (corresponding to the input range: -60dBm~0dBm).

3.3.3.2 Inverter Circuit According to the above, the slope of the input-output relationship curve of AD8318 is -50mV/dB. As the input signal power increases, the detection output voltage value decreases continuously. Since this design adopts the oscilloscope display mode, such an inverse proportional relationship is not conducive to the user's observation. At the same time, in order to reduce the possible impact of the subsequent circuit on the detection output, a first-stage op amp is added after AD8318, and the connection mode is reverse follower mode.

Since the signal frequency after AD8318 is relatively low (maximum about 60MHz), the op amp is TSH11. The characteristic of TSH11 is large input impedance, which reduces the impact on the previous stage. The connection method between the op amp and AD8318 is shown in Figure 3-8 below:

3.3.4 Data Acquisition Module

As can be seen from Figure 3-5, the signal acquisition channel mainly consists of two parts: signal conditioning channel and A/D sampling, which are introduced below.

3.3.4.1 Signal Conditioning Channel

The analog channel refers to the circuitry before the signal reaches the A/D converter after detection. The analog channel mainly controls the measured signal by AC/DC coupling, attenuation, amplification, etc., so that the signal amplitude before entering the A/D converter is within a certain range to meet the A/D converter's requirements for input analog signals. The overall schematic diagram of the analog channel is shown in Figure 3-9.

The 10-fold attenuation circuit in the channel uses a passive attenuation network, that is, it uses the principle of resistor voltage division. Such a circuit has very little loss at lower frequencies, but has large losses at high frequencies, and needs to add an RC compensation circuit, as shown in Figure 3-13. It can be seen from Figure 3-10 that the attenuation multiple is Vo/Vi=R2/R1+R2. When R1/R2=9, Vo/Vi=1/10, which means the attenuation is 10 times. In the figure, C1 and C2 are compensation capacitors, and C2 is an adjustable capacitor. Adjusting C2 can make the compensation circuit achieve the best compensation (that is, satisfying R1/R2=C2/C1).

In order to reduce the impact on the front stage, we added an impedance matching circuit after the 10 times passive attenuation circuit in our design, as shown in Figure 3-11 below. High input impedance and low output impedance are required to ensure that no distortion occurs during signal transmission. Therefore, the front stage of the circuit uses a field effect tube because it is a voltage-controlled element with a large input impedance. The second half uses a triode common collector circuit connection to ensure that the rear stage amplifier circuit works better.

Since we added a variable gain amplifier to the front end of the A/D in our design, the signal amplification capability of the amplifier circuit is not high, as shown in Figure 3-12. In order to reduce the mutual influence on the front and rear circuits, the OPA695 chip is selected here, which has a bandwidth of 1400MHz when set to 2 times amplification, a bandwidth of 450MHz when 8 times amplification, and low input voltage noise. It can play a good role in signal isolation and amplification.

In the main amplifier circuit, the voltage gain of the operational amplifier is 2. Among them, C1 is an advance compensation capacitor to prevent the amplifier circuit from self-oscillating. The main function of the drive amplifier circuit is to convert the single-ended input signal into a differential output, and add four clamping diodes to the input end so that the input voltage range is between -1.0 and +1.0. A 1V common-mode voltage is added to the input end so that the amplitude of the signal that finally enters the A/D converter is within the range of 0V to 2V to meet the requirements of the A/D converter. The schematic diagram of the drive amplifier circuit is shown in Figure 3-13. In the figure, the gain G of the operational amplifier is calculated to satisfy the following formula:

At this time, the slope of the input-output relationship curve of AD8318 is -50mV/dB, and the amplitude range of the detection output signal is 0.5V~2.5V (corresponding to the input range: -60dBm~0dBm).

3.3.3.2 Inverter Circuit According to the above, the slope of the input-output relationship curve of AD8318 is -50mV/dB. As the input signal power increases, the detection output voltage value decreases continuously. Since this design adopts the oscilloscope display mode, such an inverse proportional relationship is not conducive to the user's observation. At the same time, in order to reduce the possible impact of the subsequent circuit on the detection output, a first-stage op amp is added after AD8318, and the connection mode is reverse follower mode.

Since the signal frequency after AD8318 is relatively low (maximum about 60MHz), the op amp is TSH11. The characteristic of TSH11 is large input impedance, which reduces the impact on the previous stage. The connection method between the op amp and AD8318 is shown in Figure 3-8 below:

3.3.4 Data Acquisition Module

As can be seen from Figure 3-5, the signal acquisition channel mainly consists of two parts: signal conditioning channel and A/D sampling, which are introduced below.

3.3.4.1 Signal Conditioning Channel

The analog channel refers to the circuitry before the signal reaches the A/D converter after detection. The analog channel mainly controls the measured signal by AC/DC coupling, attenuation, amplification, etc., so that the signal amplitude before entering the A/D converter is within a certain range to meet the A/D converter's requirements for input analog signals. The overall schematic diagram of the analog channel is shown in Figure 3-9.

The 10-fold attenuation circuit in the channel uses a passive attenuation network, that is, it uses the principle of resistor voltage division. Such a circuit has very little loss at lower frequencies, but has large losses at high frequencies, and needs to add an RC compensation circuit, as shown in Figure 3-13. It can be seen from Figure 3-10 that the attenuation multiple is Vo/Vi=R2/R1+R2. When R1/R2=9, Vo/Vi=1/10, which means the attenuation is 10 times. In the figure, C1 and C2 are compensation capacitors, and C2 is an adjustable capacitor. Adjusting C2 can make the compensation circuit achieve the best compensation (that is, satisfying R1/R2=C2/C1).

In order to reduce the impact on the front stage, we added an impedance matching circuit after the 10 times passive attenuation circuit in our design, as shown in Figure 3-11 below. High input impedance and low output impedance are required to ensure that no distortion occurs during signal transmission. Therefore, the front stage of the circuit uses a field effect tube because it is a voltage-controlled element with a large input impedance. The second half uses a triode common collector circuit connection to ensure that the rear stage amplifier circuit works better.

Since we added a variable gain amplifier to the front end of the A/D in our design, the signal amplification capability of the amplifier circuit is not high, as shown in Figure 3-12. In order to reduce the mutual influence on the front and rear circuits, the OPA695 chip is selected here, which has a bandwidth of 1400MHz when set to 2 times amplification, a bandwidth of 450MHz when 8 times amplification, and low input voltage noise. It can play a good role in signal isolation and amplification.

In the main amplifier circuit, the voltage gain of the operational amplifier is 2. Among them, C1 is an advance compensation capacitor to prevent the amplifier circuit from self-oscillating. The main function of the drive amplifier circuit is to convert the single-ended input signal into a differential output, and add four clamping diodes to the input end so that the input voltage range is between -1.0 and +1.0. A 1V common-mode voltage is added to the input end so that the amplitude of the signal that finally enters the A/D converter is within the range of 0V to 2V to meet the requirements of the A/D converter. The schematic diagram of the drive amplifier circuit is shown in Figure 3-13. In the figure, the gain G of the operational amplifier is calculated to satisfy the following formula: