Implementation of a CPLD Self-Powered System

A common industrial and consumer application is a system that samples environmental conditions such as GPS (Global Positioning System) position, voltage, temperature, or light at long intervals (e.g., once a minute). Increasingly, these systems are wireless and battery powered, waking up once a minute, taking a sample, transmitting the data to a central data collection terminal, and then going back to sleep. This design idea uses a small portion of an Altera EPM240-T100 CPLD (complex programmable logic device) in conjunction with some discrete capacitors, resistors, diodes, and MOSFETs to automatically wake a CPLD system from a completely powered-off state through an RC timer circuit.

CPLD (Complex Programmable Logic Device) is a device developed from PAL and GAL devices. It is relatively large in scale and complex in structure, and belongs to the scope of large-scale integrated circuits. It is a digital integrated circuit that users construct logical functions according to their own needs. Its basic design method is to use the integrated development software platform, schematic diagrams, hardware description languages ​​and other methods to generate the corresponding target files, and transmit the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system. CPLD is mainly composed of programmable logic macro cells (MC, Macro Cell) surrounding the center of the programmable interconnection matrix unit. Among them, the MC structure is relatively complex and has a complex I/O unit interconnection structure. Users can generate specific circuit structures according to their needs to complete certain functions. Since the CPLD uses fixed-length metal wires to interconnect the logic blocks, the designed logic circuit has time predictability, avoiding the disadvantage of incomplete timing prediction of the segmented interconnection structure.

Figure 1 shows a basic CPLD on/off timer. Q1 is an IRLML6302 P-channel MOSFET that is used as the system's power control switch. When the gate node is at VCC, R2 pulls up, and the power to the CPLD and the entire system is cut off, with only the RC circuit consuming a small amount of power. The CPLD has a control block, a 4.4MHz internal oscillator, a 3-bit register, and 6 I/Os. Figure 2 shows the state machine for the control portion. The dashed line from power down to power up represents the time delay measured by the RC circuit formed by R1 and C1 when the system is powered off. The circuit is initialized when switch S1 is turned on. When S1 is closed, D2 pulls the gate node low, and Q1 turns on when the gate voltage is 0.7V below VCC. Less than 200ms after Q1 is powered on, the EPM240-T100 operates in the power-on state. The power-on state pulls the power node low, maintaining the gate voltage at 0.7V, and keeps Q1 on after the switch is opened.

Next, the sampling and transmission circuit starts working, making the done signal 0. When the sampling and transmission are completed, the done signal becomes 1, and the control block enters the save state. The save state charges the capacitor C2 to CN according to the value in Register 1. The save state is activated for 100ms, so that the output fully charges the 10mF capacitor. After 100ms, the control block enters the power-off state and stops driving the charging node and the power node. R4 pulls the power node high, and R2 pulls the gate node high.

When the gate node reaches VCC-VTQ1 at approximately 2.3V, Q1 shuts off power to the system. All I/Os of the EPM240-T100 are in a high impedance state and do not affect the gate node or the charge node. The charge node starts at VCC and begins to discharge through R1 when the power is turned off. Once the charge node drops to 2.3V, D1 pulls the gate node low. When the charge node reaches 1.6V, the gate node is at 2.3V and Q1 turns on.

The device powers up in the Power-Up state but quickly switches to the Sample state. The Sample state records the values ​​on capacitors C2, C3, and C4. These capacitors act as nonvolatile memory to store the number of previous power-up cycles. If the Register 1 value sampled on C4 to C2 is less than 7, the control block begins incrementing and the Register 1 value increases by 1. The control block then enters the Save state again and C2 to C4 charge to a new binary value of 001. The device powers down again. On the 8th power-up cycle, or about 80 seconds after power-up, the control block switches to the Enable state, thus starting a new sampling and transmission sequence. This process repeats every 80 seconds. You can change this 80-second cycle by adjusting C1 and R1 to change the size of Register 1 and the count between enable cycles. Since the 80-second cycle consists of 8 small power-up sampling, testing, and power-down cycles, the duty cycle of the power supply is less than 3%, so this scheme increases battery life by 33 times.