Design of high performance on-chip integrated CMOS linear regulator

Power management technology has been widely used in portable and handheld power supplies in recent years. Power management systems include subsystems such as linear regulators, switching regulators, and control logic. This paper mainly studies low-dropout linear regulators. Low-dropout linear regulators are a basic part of power management systems to provide a stable voltage source. They are improved efficiency linear regulators. By replacing the common-source power tubes of conventional linear regulators with common-drain power tubes, the minimum voltage drop is reduced to improve power efficiency. Since the smaller voltage drop on the power tube reduces power consumption, low-dropout linear regulators are widely used in low-voltage, on-chip integrated power management systems.

To meet the stability requirements of conventional linear regulators, a microfarad-level off-chip capacitor is usually required. Larger microfarad-level capacitors are not yet available under current design processes, so each linear regulator requires a board-level off-chip capacitor. To solve this problem, this paper proposes a linear regulator solution without an off-chip capacitor. This design removes the large off-chip capacitor while ensuring system stability under various operating conditions. Removing large off-chip capacitors not only reduces the board-level packaging cost, but also reduces the cost of the entire design, and is also conducive to on-chip integrated design.

1 Circuit Principle

Since this power converter has no off-chip capacitors, there are two main design problems: one is the transient response of the overshoot voltage, and the other is the stability of the converter. In order to solve these problems, this paper uses pseudo-Miller capacitors to improve the stability of multi-stage op amps.

1.1 Transient response compensation

In a voltage converter without off-chip capacitors, the small on-chip output load capacitor Cout cannot be used as the main pole, so it must be extrapolated to the high-frequency pole. Therefore, the main pole must be in the differential op amp loop, and the transient response signal must pass through the main pole of the loop. Figure 1 shows the linear regulator and circuit structure. In the figure, the equivalent input capacitance of the main pole is CG (≈CGS+ApassCGD+C1), and the output impedance R of the differential op amp can convert current into voltage. When the output current generates a step, the power tube can only provide the required current after a certain delay time tp and the gate voltage Vg is close enough to its steady-state voltage. The parasitic poles of the differential op amp must be extrapolated to high frequencies (this can reduce the impact of these poles on delay). The speed of the linear regulator is mainly determined by the propagation delay time tp affected by gmerror/CG, where gmerror is the small signal transconductance of the differential op amp input. Due to the limitation of the loop bandwidth, the loop fed back by the differential op amp cannot drive the gate of the power tube quickly. Therefore, a loop is needed in the design to accelerate the injection of the gate current of the power tube.


The differentiator in Figure 1 is an auxiliary fast path, which can be used as a compensation circuit and become the core component of this linear voltage regulator. The differentiator not only provides a fast transient detection path, but also serves as an AC stability compensation. In fact, the coupling network can be simply understood as a unit gain current buffer. The output voltage change induced by Cf can be converted into a current signal if, and then injected into the gate capacitance of the power tube through the coupling network. The compensation circuit separates the poles, similar to the conventional Miller compensation structure, and can also improve the speed of the loop. Assuming that the load step current is △ILOAD, it will generate an output voltage ripple △VOUT, and at the same time, the current flowing through Cf will charge and discharge Cg, thereby changing the leakage current of the MP tube to compensate for △ILOAD, and finally return Vout to its stable point. The value of the coupling capacitor required to reduce the output ripple can be obtained by analyzing the circuit in Figure 1. Assuming that the current flowing through RF1 and Rf2 is negligible, the compensation current corresponding to the change in the gate voltage of the power tube is:


For a linear regulator with a current amplitude of 0 to 50 mA and a maximum output ripple voltage of 100 mV, assuming Gmp = 50 mA/V, CG = 5 pF, and the compensation capacitor Cf is 10CG = 50 pF; then, the value of the coupling capacitor must ensure that the minimum output ripple can be maintained at no load or minimum Gmp. Therefore, more coupling capacitors are required when the load transient operating current changes from low to high.

Obviously, the required coupling capacitor is too large, which is not conducive to on-chip integration. Therefore, a technology is needed to reduce the size of Cf and maintain effective coupling capacitance. To analyze the circuit, Figure 2 shows a simple open-loop equivalent circuit diagram. If the impedance of the resistor is smaller than that of the capacitor, the current flowing through the capacitor will be converted into a voltage through the resistor RZ, and then converted into a current through Gmf. The auxiliary circuit composed of a pseudo-differential circuit can increase the effective compensation capacitance in the following ways:


In the above expression, it is assumed that the parasitic pole 1/RzCf is located in the high frequency range. The role of Gmf will be reflected in two aspects: first, Cf can be reduced in magnitude through GmfRz, and second, the influence of the feedforward path caused by Cf capacitance can be eliminated.

1.2 AC stability analysis

The transfer function can be obtained through Figure 2(b). The parasitic pole 1/RzCf of the differentiator is extrapolated outside the loop unit gain bandwidth, while ignoring its influence, and assuming that the Miller capacitance CG=Cgs+Apass-CGD, and then using the standard circuit analysis model, the open-loop transfer function can be obtained as:

The above equations describe the ideal effect of the differentiator and quasi-Miller compensation. The location of the zeros and poles can be simplified by assuming that CfRzGmfR1GmpRout>>CoutRout1+CGR1. This gives:

As we hope, the differentiator can separate the input pole and output pole of the power tube, but it does not introduce a zero point in the right half plane. The high-frequency coupling loop gain GmfRz can ensure that the two poles are far enough away and make the linear voltage regulator stable.
 
Figure 3 shows a complete small signal circuit model, which modifies the differentiator into a transistor model application. It adds a secondary differential op amp stage GmE. The compensation circuit is composed of a differentiator (Cf, RF and Gmf1) and an additional cross-inverted op amp Gmf2 to increase the feedback gain, thereby obtaining a larger equivalent capacitance Cf,eff (≈Gmf2RfCf). This feedback loop also includes feedback resistors Rf1, Rf2 and their parasitic effects. However, the differentiator introduces parasitic poles ωPD1 and ωPD2 at the Vx and Vr points respectively, which affects the AC stability of the entire loop. Therefore, these two parasitic poles should be extrapolated during design to keep the system loop stable.

When analyzing the zeros and poles of a complex circuit, we can first determine that the main pole is the power tube gate point Vg, which is at a very low frequency. The secondary pole is the output node Vout. Other parasitic zeros and poles include the poles introduced by the differentiator and the zeros introduced by the power tube Cgd. By extrapolating these zeros and poles to 5 to 10 times the loop bandwidth, we can get a better phase margin.

2 Transistor-level circuit design


The transistor-level circuit is shown in Figure 4. In the figure, the three-stage current mirror operational transconductance amplifier M0-M3 and ME constitute a differential operational amplifier.


The internal nodes of the three-stage Miller current transconductance operational amplifier are low impedance, so that the part of each parasitic pole above the unity gain bandwidth of the loop is extrapolated to the high frequency range. Extrapolating the parasitic pole of the differential op amp to a frequency range of more than 3 times the loop bandwidth can reduce the impact of the parasitic pole on the performance of the regulator. The differentiator can compensate for the transient response of the load output. Its feedback input node is Mgmfl, which is the first stage op amp of the differential converter and a very critical node. Generally, sufficient gain is required to drive the differential capacitor to extrapolate the generated poles ωPD1 and ωPD2 to higher frequencies, but very small parasitic capacitance will also be generated. Therefore, the compromise between transient response and loop stability is a rather difficult problem. Rf can convert the current flowing through the capacitor Cf into a voltage when the output current changes transiently, and DC bias the Mf1 and Mf2 tubes. In addition, it can reduce the input impedance of the differentiator, thereby extrapolating its related pole ωPD1 to outside the loop gain bandwidth. The differential converter can be combined with the differential op amp through transistors Mf2 and M4. In order to improve the AC stability by adding the compensation capacitor Cf3, the input pole of the differentiator can be extrapolated to a higher frequency range by using the Miller effect of Cf3.

The design can start with the output voltage drop VDROP and the maximum load current, and define the parameters of the power tube, then define the parameters of the differentiator, then determine the parameters of the differential op amp, and finally select the compensation capacitor Cf3. Figure 5 shows the circuit Spice simulation results under three load conditions. In the temperature range of -25 degrees to 75 degrees, the loop gain bandwidth of the unbiased external capacitor linear regulator is greater than 1MHz, and its phase margin can exceed 50 degrees. For smaller load capacitance, the unity gain bandwidth of the loop and the stability of the circuit will be improved.

3 Analysis of simulation results

The design of the entire LDO can be realized using SMIC 0.13μm CMOS process. The area is 0.22 mm2, the static current is 300μA, the on-chip capacitance is 100 pF, and most of the layout area is on-chip capacitance and power tube. When the load transient current changes from 0 to 50 mA and the current rise and fall time is 1 μs, the simulation results shown in Figure 6 will appear.

　
As shown in Figure 6, when the load current changes from 0 to 50 mA, the output voltage ripple is 84 mV and 59 mV respectively, and the lock time is about 4 μs. When the load current changes from 10 to 50 mA, the output ripple is less than 20 mV. The turn-on time of the regulator is less than 10 μs. When the load current is 10 mA and the input sinusoidal signal is applied to the power supply, the power supply rejection ratio (PSRR) of the linear regulator is -50 dB at 100 kHz and -53 dB at 1 kHz.

4 Conclusion

The simulation results show that the proposed linear regulator without external capacitors can show good transient response and stability among similar products at the expense of some static power consumption, and its on-chip capacitance can be reduced as the load capacitance increases. Therefore, under the condition of ensuring loop stability, the load capacitance can change in a large range. The proposed linear regulator without external capacitors can simplify and reduce the design and cost of test boards and packages. Therefore, it can be widely used in the design of on-chip systems.