Circuit Design of LCD Power Management

1 Introduction

To realize the display of liquid crystal display, the following four units are required: controller, power management unit (PMU), driver circuit, liquid crystal display device (LCD). For liquid crystal display devices with smaller resolution, such as 128×64, 128×32 and other modules, there are chips that integrate controller, power management unit and driver. However, for high-resolution liquid crystal display (such as 320×240, 640×480), separate controller, power management unit and driver are required. This paper gives a design scheme of power management circuit for high-resolution liquid crystal display.

2 Circuit design scheme

To realize liquid crystal display, four units are required, and its block diagram is shown in Figure 1. The power management circuit design scheme given in this paper has the functions of driving voltage generation, timing control, temperature compensation and contrast adjustment, and its block diagram is shown in Figure 2.

Figure 1 Block diagram of the four units of the LCD system

2.1 Driving Voltage Generation Circuit

LCD display requires not only logic power supply but also driving power supply. The driving power supply varies with different driving chips. This article takes the HT66130/HT66137 of Hitachi, Japan as an example. This series of chips is a chip for driving high-resolution LCD displays, and the required driving voltages are VLCD, V0, and VM3. Since the duty cycle is 1/240 and the VLCD voltage is above 15V, we use the DC/DC device MAX1606 of Maxim to generate a 15.9V VLCD voltage, and obtain V0 and VM through resistor voltage division. V0 and VM are then provided to HT66130 and HT6613 through operational amplifiers, as shown in Figure 2.

Figure 2 LCD power management block diagram

2.2 Timing Control Circuit

All LCDs have strict requirements for power-on and power-off timing. If the power-on and power-off timing do not meet the requirements, the display cannot be normal, and garbled characters, latching, residual display and other phenomena often occur. Taking the Japanese Hitachi driver chip HT66130/HT66137 driving a 320×240 LCD display as an example, the requirements for power-on and power-off timing are shown in Figure 3, and the requirements for general LCD driver chips are roughly the same.

Usually, the power management circuit of the LCD monitor relies on the CPU to use software to control the timing of the signal to ensure the power-on and power-off timing requirements of the LCD display device. This occupies more general input and output ports (GPIO), and the software has not yet run at the moment of power-on, and can only rely on the default state of the CPU's GPIO to control. At present, dual-CPU systems such as smart phones are more difficult to control by software. The circuit designed in this article only needs one GPIO (i.e., the display enable signal DISP) to control the power-on and power-off timing and the switch of the driving power supply, and there is no timing requirement for DISP.

Figure 3 Hitachi HT66130/HT66137 timing diagram

For the power-on timing, generally, there must be a frame frequency initialization time before the display enable signal can be set to a high level. The traditional approach is to rely on the CPU's GPIO port delay to control. The circuit designed in this article uses a D-type flip-flop, and uses the frame frequency signal (FRAME) as the clock input, the display enable signal (DISP) as the D input and controls the CLEAR end, and the Q end output controls the switch of the entire drive circuit. In this way, the timing control of the DISP input can be realized, and the DISP can be used to control the switch of the entire drive power circuit. Since the DISP can turn off the drive circuit, the standby state can be realized. The power consumption of the drive circuit is very small, and there is only the static current of the trigger and gate circuit. In order to meet the DISP signal input after the drive voltage is stable, we use the AND gate to control the DISP and the drive voltage input to realize the DISP output.

When powering off, the timing of the display enable signal, drive power, display clock/data signal, and logic power must be strictly followed. In order to meet the power-off timing requirements, the CPU's GPIO is generally used for control. This design uses a D flip-flop and an AND gate to realize that the DISP is set low in advance of the drive voltage. The DISP signal is used to control the power supply circuit. When DISP is set low, the driving power supply of the HT66130/HT66137 driver chip is completely turned off, and no additional GPIO port is required for control. The test shows that the circuit operates normally and can effectively control the timing of power on and off, without garbled code, latching, residual display and other phenomena. Moreover, the power consumption of the driving circuit in the standby state is very small, only 0.2 mW (including circuit and LCD display device).

2. 3 Temperature compensation circuit

In order to ensure that the LCD display can work normally in a wide temperature range, the temperature compensation circuit is very necessary. The driving voltage and temperature characteristics of the LCD screen used are shown in the solid line of Figure 4. Therefore, the circuit design is optimized by using the temperature characteristics of thermistors and the series-parallel relationship of resistors. The specific circuit is shown in Figure 5. R1=638 kΩ, R2=110 kΩ, R3=62 kΩ, and the characteristics of RTH are shown in Table 1. The calculation formula of R1, R2, R3, RTH and DC/DC (MAX1606) output voltage is:

Figure 4 LCD screen temperature compensation curve

2.4 Contrast Adjustment Circuit

The contrast adjustment of the LCD can be divided into hardware adjustment and software adjustment. The circuit in Figure 5 has both software and hardware adjustment functions. R1 is an adjustable resistor that can adjust the voltage of VLCD, so that the contrast of the LCD can be adjusted; the circuit can also use the CPU combined with the digital-to-analog converter (DAC) to control the voltage at the feedback end of the DC/DC, so as to achieve software adjustment of the contrast of the LCD.

Figure 5 Temperature compensation/contrast adjustment circuit

3 Software Flowchart and Display Effect Diagram

The test flow chart of LCD startup and shutdown is shown in Figure 6. The initialization of the LCD controller is the most important, and the CPU registers and delay time must be configured according to the requirements of the LCD display module.

Figure 6 LCD display software flow chart

4 Conclusion

The actual test shows that the circuit operates normally and can effectively control the timing of power on and off. The power consumption of the drive circuit in the standby state is only 0.2mW. The temperature compensation characteristics are good. Both software and hardware can adjust the contrast of the LCD display.