Analyzing Power Consumption and Power Integrity of FFT Chips Using Astro-Rail

Introduction

The Astro-Rail tool provides chip designers with the ability to perform power consumption, voltage drop, and electromigration analysis during the design and sign-off phases. It takes less than an hour to use the Astro-Rail tool to perform power consumption, voltage drop, and electromigration analysis on a 5 million gate design. After the analysis is completed, Astro-Rail clearly displays the areas that may have problems in different colors on the layout to help designers analyze and find problems. The sign-off analysis results it provides are less than 5% different from the results of Star-RCXT back-annotation and re-analysis. Astro-Rail is an important component of the Synopsys Galaxy platform. It uses unique dynamic macromodule technology to achieve a breakthrough speed, which is 2 to 3 times the speed of general rail analysis tools. The

FFT chip in this article is a 16-bit 128-point FFT/IFFT fixed-point processor. The processor is mainly used in OFDM-based UWB systems and uses the N=4×4×4×2 algorithm to implement fixed-point FFT operations. It uses a two-stage pipeline structure, including three stages of radix-4 operations and one stage of radix-2 operations. The clock frequency of this design is 62MHz. It uses SMIC 0.18mm 1P5M CMOS process. The Astro tool is used to complete the 3.7mm×3.7mm layout area floor plan, power ring and power bar pre-routing, and the PC tool is used for timing and blocking-based layout. The Astro tool is then used
to complete clock tree synthesis and routing. Under the condition of meeting static timing analysis and design rule checking, the Astro-Rail tool is used to perform power consumption analysis on the FFT chip to determine whether the number of pad pairs of power and ground meets the requirements. The voltage drop and electromigration analysis is used to determine whether the wiring of the power ring and power bar meets the voltage drop and electromigration requirements. The

Astro-Rail method for analyzing gate-level power consumption

uses the Astro-Rail tool to analyze gate-level power consumption, which includes four parts: switching power, short-circuit power, internal power, and leakage power. A capacitor is formed between the output end and the ground of the

switching power

unit gate device. The power consumed by charging or discharging the capacitor when the device is turned on or off is the switching power. The formula for Astro-Rail to calculate switching power is: P=C×V2×f/2. Where f is the signal transition rate, that is, the number of times the signal transitions between high and low levels per unit time; C is the line load capacitance at the output of the gate device, and its value can be extracted through the line load model or from the layout after the physical design is completed. The latter has higher accuracy; V is the power supply voltage.
Short-circuit power

When the state of a unit changes from 0 to 1 or from 1 to 0, the corresponding N-type and P-type tubes are turned on at the same time in a short period of time, thereby generating a path from the power supply to the ground in the unit gate device. The power consumed in this process is called short-circuit power.

Internal power

For a unit gate device, not every change in the input signal state will cause the output signal state to change. The power consumed when the input signal state changes but the output signal state remains unchanged is called internal power. Taking the two-input OR gate as an example, when both A and B inputs are 1, the output X is 1. At this time, if the input B changes from 1 to 0, the output X state remains unchanged, but the state of the tube controlled by input B changes, thereby consuming internal power.

Leakage power

Leakage power refers to the power consumed when the transistor is not switching. Although there is leakage current in some reverse-biased diodes between the transistor drain and the substrate, most of the leakage power comes from the subthreshold current when the transistor is turned off. When a design has been determined, its leakage power is constant and has nothing to do with the working state of the chip.

Power consumption analysis of FFT chips

The process of Astro-Rail analyzing the power consumption of FFT chips mainly includes 5 steps.

View the process library file

View the defined units of voltage, power consumption, current, etc. in the smic18_apollo_m5.tf process library file, and search for the maximum current density value of each metal layer and each via by searching for the keyword maxCurrDensity.

Create an LM directory in the Milkyway environment

The Milkyway environment is a database established by Synopsys for ultra-deep submicron (nanoscale) design, which greatly facilitates the entire physical design implementation process. The LM directory provides the necessary timing information and power consumption information for the Astro-Rail tool to analyze gate-level power consumption, voltage drop, and electromigration. Since the SMIC 0.18mm CMOS process does not have an LM directory in the Milkyway environment, it is necessary to use the gePrepLIbs command in the Astro environment to create an LM directory. The specific method is: in the STD (standard cell library) directory, enter the Astro environment, enter the gePrepLIbs command, and after execution, a dialog box will open. In the dialog box, make the corresponding settings to generate the LM directory of STD. Use the same method to create the LM directory of standard IO.

Import the voltage value of the VDD network

. The Astro-Rail tool uses the voltage value of VDD to calculate the power consumption of the chip. The default value is 0V. The command to specify the voltage value of the VDD network is:

tdfSetPowerSupply "VDD" 1.62 1.8 1.98

Save the command in the Powersupply.tdf file, and then execute the poLoadPowerSupply command. A dialog box will pop up to enter the file for import.

Import the signal transition information of the chip

. In order to correctly analyze the power consumption of various unit gate devices, the key is to accurately calculate the signal transition rate of each unit gate device. For the 0.18mm process used in this article, the power consumption of the chip mainly depends on the dynamic power consumption, and the dynamic power consumption depends on different input vectors. It is usually necessary to design a large number of input vectors for simulation for each part of the chip to record the signal transition information. The signal jump information is recorded by the Value Change Dump (VCD) file. When importing the chip's signal jump information, first execute the menu command Power>Load NetSwitching Activity, select VCD mode in the input format of the pop-up dialog box, then enter the VCD file name and press the OK button to import.

 

Power consumption calculation

Execute the menu command Power>Power Analysis, make appropriate selections in the pop-up dialog box, and press the OK button to calculate the power consumption of the FFT chip. The results are as follows: the switching power is 293.88mW, the short-circuit power is 293.991mW, the internal power is 160.541mW, the leakage power is 0.1159mW, the total power consumption is 748.527mW, and the total current is Itotal=415.848mA. According to the process library document: the maximum current allowed to pass through the power and ground PADs is Imax=51mA, so the minimum number of pairs of power and ground PADs n can be determined:

n= Itotal/Imax=415.848/51=8.15

In the FFT chip of this article, 12 pairs of power and ground PADs are arranged, so it meets the requirements. In the design, several pairs of power and ground PADs should be placed, which can not only reduce voltage drop, but
also reduce parasitic capacitance with redundant power, ground PADs and bonding wires, thereby reducing voltage fluctuations caused by current changes.

FFT chip voltage drop and electromigration analysis

Chip power integrity analysis includes voltage drop analysis and electromigration effect analysis. Voltage drop analysis includes calculating the voltage drop to the power network VDD and the voltage rebound value to the ground network GND. The voltage drop to the power network VDD is caused by the metal connection resistance of the power network in the chip, resulting in a decrease in the potential difference between the power supply and the ground; the voltage rebound to the ground network GND is mainly caused by the inductance of the switching current flowing through the connection or substrate, and may also be caused by the package lead inductance connecting the power supply and the ground. Voltage drop and ground voltage rebound will reduce the noise margin of the logic gate and increase the delay. Electromigration is caused by the high-density current in the metal connection, which forms a flow of metal conductive atoms between the positive bias end and the negative bias end of the metal. This strong atomic flow may cause metal breakage (metal wire open circuit) or extrusion (metal wire short circuit). Therefore, it is necessary to perform voltage drop analysis and electromigration analysis on the FFT chip after completing the power consumption analysis.

Extracting power and ground network parameters

To correctly analyze the voltage drop, it is necessary to extract the resistance and capacitance values ​​of the power and ground networks. Execute the poPGExtraction command, open the dialog box, select VDD in the PG net name and press the Apply button, then select GND and press the OK button to complete the power and ground network parameter extraction.

Define the ideal power input point

In the process of analyzing voltage drop and electromigration, use the poGenUserDefineTap command to automatically generate user-defined ideal source input points. The specific method is: first execute the poGenUserDefineTap command, a dialog box pops up, then click the Layer panel option on the shortcut button on the left side of the FFT layout window, and select to display only the M1 layer (layer number 61) in the pop-up dialog box. Click the left mouse button at the connection point between each VDD PAD and the VDD network line, and the point position will be automatically added to the vddtaps file and displayed in the command window: Writing tap (VDD 61 336.750 3514.180) into file "vddtaps". Use the same method to define the ideal voltage input point file gndtaps required for analyzing ground voltage rebound.

Calculate the maximum voltage drop

Enter the poRailAnalysis command, a dialog box pops up, select the user-defined Tap in P/G pad info, enter the file name vddtaps in the user-defined Tap file, and select the Extract Option option to analyze the voltage drop. From the analysis results, it can be seen that the maximum voltage drop is 70.726mV, which is less than 0.1VDD, that is, 180mV, proving that the layout of the FFT chip power ring and power strip meets the voltage drop requirements. To

calculate the maximum ground voltage rebound, just enter the file name gndtaps in the user-defined Tap file and select the Extract Option option to analyze the ground network. From the analysis results, we can see that the maximum ground voltage rebound is 46.419mV, which is less than 0.1VDD, i.e. 180mV, which proves that the layout of the FFT chip power ring and power strip meets the ground bounce voltage requirements.

Display voltage drop map

When the track analysis is completed, different colors can be used to display the voltage drop of different parts of the chip FFT. The specific method is: execute the menu command Power>Display Voltage Drop Map…, a dialog box pops up, select VDD for analysis in PG Net, and press the Apply button to automatically specify the maximum voltage drop value of -70.726mV. Divide the maximum voltage drop value -70.726mV into 12 equal parts, and select each equal division range and corresponding color configuration to be displayed on the FFT chip layout. Press the OK button to get the voltage drop map, as shown in Figure 1. From the figure, it can be seen that the voltage drop corresponding to the egg-shaped area in the middle is large, and the highlighted small rectangle in this area indicates that the VDD network voltage drop here is the largest. The ground level rebound map can be analyzed in the same way.

Figure 1 FFT chip voltage drop diagram

 

Displaying the electromigration map

The electromigration map can use different colors to display the current density of each layer of the chip and the vias in different parts of the chip FFT. The specific method to display the electromigration map is: execute the Power> Display Electromigration Map… menu command, a dialog box pops up, select VDD for analysis in PG Net, and then click the Color, Metal, Via Bounds button to open the dialog box shown in Figure 2. The maximum current density allowed for each metal layer and via in the dialog box is automatically filled in according to the specifications in the smic18_apollo_m5.tf process library file. The maximum current density allowed for each metal layer and via can be modified according to actual conditions.

Select the M1 metal layer in Figure 2 and press the OK button for analysis to obtain the electromigration map of the M1 layer, as shown in Figure 3. 12 different colors can be used to display the current density of different parts on the FFT chip layout. As can be seen from the figure, the parameter value range of the area with larger electromigration rate in the M1 layer is 6.667~7.5, which is less than the maximum current density of 10 allowed by the M1 layer. The same method can be used to analyze the electromigration diagrams of other metal layers and vias. It can be determined from the diagram that the electromigration rates of each metal layer and via are less than the maximum allowable current density, thus proving that the layout of the FFT chip power ring and power bar meets the electromigration requirements.

Figure 2 Maximum current density allowed for metal layers and vias

Figure 3 FFT chip M1 layer electrical mobility diagram

Conclusion

With the continuous improvement of integrated circuit manufacturing technology, the integration is getting higher and higher, and the corresponding power consumption, voltage drop and electromigration problems are becoming more and more prominent. The method of reducing chip power consumption is related to the design; the main method to solve the voltage drop is to increase the width and number of power lines and ground lines, and arrange the power network reasonably; the main method to solve the electromigration problem is to increase the number of power and ground PAD pairs, increase the width and number of power lines and ground lines, and set wider connections for critical paths. By using the Astro-Rail tool to extract parameters of the power and ground networks, and then calculate power consumption, voltage drop and ground bounce voltage, and display the results of voltage drop and electromigration analysis, it can ensure that the number of power and ground PAD pairs related to power consumption in the chip, and the voltage drop, ground voltage bounce and electromigration effects related to the layout and wiring of the power ring and power strip are solved.

References

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3. DjavadAmiri, WeihuaMao. Enabling Low Power Design with Power Compiler and PrimePower [R]. Boston: SNUG, 2000

4. John P.Uyemura, translated by Zhou Runde. Introduction to Very Large Scale Integrated Circuits and Systems [M]. Beijing: Electronic Industry Press, 2004.1