Synchronous Sampling Converter AD7262

1 Overview

AD7262 is a successive approximation (SAR) analog-to-digital converter (A/D converter). It has two tracking and holding amplifiers, two 12-bit synchronous sampling A/D converters, two programmable amplifiers, two groups of comparators and two independent data output pins. It is suitable for the field of automotive control and weak signal detection applications that require high synchronization and simple calculation. Therefore, the principle and application of the synchronous sampling MD converter AD7262 are introduced in detail here.

2 AD7262 Introduction

2.1 Main Features

AD7262 has high-speed and low-power synchronous sampling, up to 1 MS/s. Its internal integrated programmable amplifier PGA has 14 amplification gains to choose from. Two groups of comparators A, B and C, D are used as operators for motor control or various electrode sensors. Among them, comparators A and B have low power consumption characteristics, and comparators C and D have high speed characteristics. Dual-channel differential input simultaneous sampling and A/D conversion, input impedance greater than 1 GΩ. Single power supply +5 V. The PGA gain is 2, -3 dB bandwidth is 1.7 MHz, and the signal-to-noise ratio (SNR) is 73 dB; when the gain is 32, the signal-to-noise ratio is 66 dB. The input DC leakage current is ±0.001μA, and the offset drift is 2.5μV/℃. It has a serial peripheral interface SPI, which is compatible with QSPI, MICROWIRE, and DSP. The device has multiple energy-saving modes, dynamically matches the required internal modules, and has two working modes: register control and pin drive.

2.2 Pin Functions

AVcc: Analog power input, 4.75~5.25 V;

CA_CBVCC/CC_CDVCC: Power input of comparator, 2.7~5.25 V;

CA_CB_GND/CC_CD_GND: Ground input of comparator;

VA+/VA-,VB+/VB-: Differential analog input of A/D converter A and B channels;

VREFA/VREFB: Reference voltage input and output of A/D converter A and B channels;

SCLK: Serial clock, SPI communication clock, and also the clock source of A/D conversion process;

CAL: Initialize internal offset calibration logic input;

PD2: Power saving mode selection logic input;
 
PD1: Power saving mode selection logic input;

PD0/DIN: Power saving mode selection logic input, and also the data input in register control mode;

CS: Chip select input;

CA+/CA-,CB+/CB-: Differential input of comparator A and B;

CC+/CC-, CD+/CD-: differential inputs of comparators C and D;

AGND: analog ground input;

DGND: digital ground input;

COUTA~COUTD: comparator CMOS push-pull output, digital output when using VDRIVE;

DOUTA/DOUTB: A/D conversion serial data output;

G0~G3: gain multiple logic input, when all are low level, register control working mode;

VDRIVE: logic power input, 2.7~5.25 V;

REFSEL: reference voltage selection terminal, high level uses internal reference voltage, low level uses external reference voltage.

2.3 Internal structure

　　Figure 1 is the internal structure of AD7262. After the two differential signals are synchronously sampled and amplified by their respective PGAs, they enter the tracking and holding device. At this time, the control logic controls two 12-bit successive approximation A/D converters to realize analog-to-digital conversion, and finally the output driver drives the output to DOUTA and DOUTB in series.

In the pin drive mode, G0~G3 must have at least one high level. The external G0~G3 determines the amplification factor of the PGA. The 3 port levels of PD2~PD0 control the use or shutdown of each module of its internal comparator and 12-bit A/D converter. In the register control mode, PD2, PD1, G0~G3 are all low levels. PD0/DIN is the data input terminal, which is used to write the relevant control register to dynamically configure the amplification factor, calibration and power saving mode. AD7262 outputs the conversion result in 2's complement.

2.4 Automatic calibration

Automatic calibration is one of the main features of AD7262. Use the CAL pin to calibrate the device offset. Set CAL to a high level and complete the initialization calibration value at the next CS falling edge. The completion of the offset calibration requires a complete conversion cycle, including 19 SCLK cycles after the CS falling edge. If necessary, CAL can remain high for more than one conversion cycle, and the AD7262 continues to calibrate at this time. The control register initial calibration value can also be used, and the CAL bit of the control register can be set to 1 to achieve it. Note that at the next CS falling edge, calibration will be initialized, and the current conversion of AD7262 will lose its meaning. Its A/D converter must be in working state to complete internal calibration.

A/D converter A and B channels have independent external gain registers to calibrate signal gain. The gain calibration register has 7 bits, which are changed to compensate for gain. MSB is the sign bit, and the other 6 bits are used to store gain multiples, which are used to adjust the range of analog input signals. Its calibration accuracy is 1/4 096.
3 Typical Application

3.1 Hardware Design

Figure 2 is a typical application circuit of AD7262 and ARM processor LPC2378, which realizes the acquisition of electrode A, B current and electrode M, N voltage in DC electrical exploration. Metal film resistors are used as sampling resistors to improve measurement accuracy. Since the voltage between electrodes A and B is the electrode voltage powered by the earth, which is generally greater than 100 V, there are high-voltage isolation circuits in the front-end electrodes, and the resistance of the sampling resistor is generally less than 100 Ω. AD7262 works in register control mode. Under the control timing of SCLK provided by P0.15 of LPC2378, relevant data is written to the control register of AD7262 through P0.18. After CS enters the low level state, P0.18 first writes the relevant register data, and then starts sampling, holding and converting the output. When writing the register, DOUTA and DOUTB outputs are tri-state. The

main communication mode of AD7262 is SPI four-wire. Since AD7262 cannot control when to communicate, it can only work in slave mode. P0.15 of the master controller LPC2378 provides the communication clock signal SCLK. CS is the chip select input. DOUTA or DOUTB is the data output terminal of SPI. The data input terminal of SPI is PD0/DIN. When designing the circuit, relevant data is written to the AD7262 through LPC2378 to realize various dynamic configurations. Figures 3 and 4 are the serial interface read and write timing diagrams. The serial clock SCLK provides the conversion clock and the control of the transmission information after the AD7262 conversion. For the two A/D converters on the chip, AD7262 has two corresponding output pins. Data is read from DOUTA and DOUTB of AD7262. Users can select one of the output data.




At the falling edge of CS, the track-and-hold is in hold mode. At this point, the analog input is initialized for sampling and conversion. This requires at least 19 SCLK cycles. When the 19th SCLK falling edge arrives, the AD7262 returns to the tracking mode and sets DOUTA and DOUTB to enable. The data stream consists of 12 bits, with the MSB first. The conversion result MSB is read by the microcontroller at the falling edge of the 19th SCLK cycle at the falling or rising edge of the 20th clock SCLK. The rising or falling edge depends on the frequency of the SCLK used. For example, when the maximum SCLK frequency is 40 MHz, its data reading time is 23 ns, resulting in a 2 ns setup time. This 2 ns setup time cannot match the microcontroller. In this case, it is necessary to start reading data at the rising edge of the clock SCLK. In this way, the MSB bit of the conversion result is delayed by 15 ns at the 19th SCLK falling edge and is read out at the rising edge of the 20th cycle SCLK. And so on, the A/D converter outputs LSB at the 30th SCLK falling edge and reads out at the 31st SCLK rising edge. On the contrary, if SCLK is 32 MHz, the falling edge reads data. In the design, the SPI communication clock frequency (P0.15 of LPC2378) is less than 32 MHz, so LPC2378 reads and writes data at the falling edge of the clock. In order to improve the accuracy and stability of the system, a coupling capacitor with a certain resistance value can be added.

3.2 Software Design

AD7262 contains 6 registers, namely the result register of the A/D converter, the control register, the internal offset register of the A/D converter A and B, and the external gain register of the A/D converter A and B channels. The control register has a total of 12 bits, of which RD3~RD0 are register selection bits. Since

both LPC2378 and AD7262 are compatible with the SPI interface, the programming of both only needs to follow the timing diagram. In addition, LPC2378 has many other types of interfaces, so it is easy to realize networking. For detailed process, see Figure 5.


Note that the CAL pin must be kept high for at least 2μs before CS is low to ensure the accuracy of calibration in the first conversion cycle. If CAL is low during this period, the calibration result will be inaccurate. But if it continues to be high, the next calibration conversion will be accurate. In addition, if CAL is high during the A/D conversion process, the conversion result will also be incorrect. The calibration of AD7262 is performed during the measurement process and before the A/D conversion. During the measurement process, calibration is performed first and then sampling and holding. Separate the timing from programming and writing registers. In addition, when using the SPI interface, hardware reset alone is not enough, and software reset is also required to ensure the correctness of the read and write data. In practical applications, the ground lines of the digital and analog parts should be isolated. The entire software part is completed by serial port reading and writing registers.

4 Conclusion

Compared with other A/D converters, AD7262 has the characteristics of fast conversion speed, simple interface, low power consumption, and strong control function. It also has the characteristics of built-in PGA, automatic calibration, synchronous sampling, etc. It is suitable for signal detection, control and motor control systems of various electrode sensors with different signal strength levels. At present, the system has been successfully applied to physical exploration electrical experimental instruments to achieve synchronous voltage measurement of AB and MN electrodes with good results.