Analysis of LDO power management module and its application in digital analog RF system

　　With the rapid development of portable and single-soldier backpack equipment in the past few decades, how to integrate various power outputs in a limited board space and control and manage them very accurately has become a problem that every hardware engineer has to face. Low voltage difference, high efficiency, smooth dynamic response, stable and pure voltage output, and the ability to effectively suppress the very "dirty" noise from the public power grid, etc., are more stringent indicators than one another, but they constitute a stable and safe energy supply platform for an excellent and complete electronic system. The standard chips in the industry, such as LM317 and LM340, can no longer meet our ever-changing requirements. The excellent and easy-to-use LDO voltage regulator chips launched by ADI, such as ADP170 and ADP1706 suitable for the digital field and ADP121 and ADP130 in the analog RF field, have become important choices for us to design power management systems.

　　LDO is composed of a reference voltage (band refence), an error amplifier, a feedback resistor voltage divider network, and a pass transistor (pass transistor). The specific structural block diagram is shown in Figure 1.

Figure 1. Block diagram of an LDO using low dropout technology to stabilize the output voltage

　　The output current I (L) is determined by the load but is provided by the pass transistor. The gate voltage of the pass transistor (we assume it is a PMOS transistor here) is controlled by the output of the error amplifier (i.e., error amplifier). The feedback voltage from the resistor divider network is compared with the standard reference voltage generated by the bandgap reference source to generate the input signal of the error amplifier. If the feedback voltage of the voltage divider network is greater than the reference source voltage, since the feedback voltage here is connected to the inverting terminal of the amplifier, the output of the error amplifier at this time is a negative value, thereby reducing the control voltage of the pass transistor to control a smaller output current. The feedback voltage is reduced through the resistor divider. The formation of this feedback loop ultimately makes the feedback voltage equal to the reference source voltage at the input of the error amplifier, stabilizing the output voltage at a fixed value.

　　From the perspective of the power management system, the loads are of different sizes and phases. At the same time, such loads are indeed time-varying. In order to achieve low-carbon energy saving for the entire system, intelligent dynamic "enabling" loads is an important means. In a large system, especially in portable devices (as shown in Figure 2), not every part of the circuit works at full load at the same time or in the same period of time. Therefore, it is necessary to "enable" various loads in sequence within the time stamp, after all, the battery energy is limited.

Figure 2 Power management module in a portable system

　　If a digital system (such as a microprocessor or DSP) is supplied with power, such a power load has a very important characteristic that must adapt to its rapidly changing instantaneous current. As we all know, whether it is an MCU or a DSP, it is not always in working state. Sometimes it is enabled and works at full load. Sometimes, even if it is enabled, only part of the circuit is in working state, and the rest is dormant to save energy. For the power chip that supplies energy to it, the impedance presented by the load each time the state switches has obvious differences in both the imaginary part and the real part. At the same time, the change between each state is very fast in time. This characteristic makes the current jump of the load very fast, which increases the transient response requirements of the power chip to the load change. Digital linear regulators such as ADP170 and ADP1706 are designed to support the main digital requirements of the system, usually the microprocessor core and the system input/output (I/O) circuit.

　　How to resist noise interference and suppress higher power ripple has always been a point that needs to be paid attention to in analog system design, and it is no exception for power management systems. As we all know, the public power grid is very "dirty" and contains a lot of noise. How to effectively suppress the interference from upstream power clutter is an important aspect to be considered by a power management system (PMS). At the same time, it should not add too much noise, thereby causing unnecessary impact on the downstream supply load. Analog regulator noise is measured by voltage effective value (rms), which should be less than 35 mV when used for sensitive circuits. PSRR reflects the ability of LDO to suppress upstream noise on the power line and should be higher than 60 dB. The ultra-low noise LDO ADP150 has an output noise of 9 mV and a PSRR of 70 dB, making it an ideal power supply device for powering sensitive analog circuits. Adding external filters or bypass capacitors can also reduce noise, but it will increase cost and PCB size. Careful and flexible LDO internal design also helps noise reduction and power supply noise suppression.

　　Finally, we must pay attention to relevant parameters when using LDO chips, such as ambient and junction temperature range, load changes, transient signal rise and fall time, and bandwidth, etc.