Description of Single Frame and Feedforward Functions of Digital Power Controller UCD3138

UCD3138 is the latest generation of digital power controller launched by Texas Instruments, which was officially released in the first quarter of 2012. Compared with the previous generation of digital power controller UCD30xx, it has important improvements in many aspects, richer functions and more powerful performance. This article is based on a switching power supply using a hard-switching full-bridge (full-wave synchronous rectification on the secondary side) topology, and introduces the Single Frame function and input voltage feedforward function of UCD3138 in detail. While completing the understanding of the above functions, you can also clearly understand the advantages of UCD3138. The last part of this article gives references.

1. Single Frame Function Design and Implementation

Single Frame is a new method to detect the input voltage on the primary side on the secondary side. This method can detect the current input voltage directly and quickly on the secondary side to achieve undervoltage protection, so there is no need for additional input undervoltage protection circuits and optocouplers or digital isolators.

1.1 Single Frame Function Introduction

Before the power system is officially running, the UCD3138 chip will periodically send out a single or several drive pulses to make the hard-switched full bridge work for a single or multiple cycles. At this time, a voltage can be generated at the center tap of the secondary side of the transformer. This voltage is linearly related to the input voltage. Therefore, the input voltage can be obtained by detecting the voltage at this point through UCD3138 and calculating it through software. Based on the calculation result, the system can determine whether the input voltage has reached the start-up point to decide whether to exit the undervoltage protection and start normal operation.

In practical applications, in order to ensure that the upper tube on the primary side of the full bridge (the driving ground is floating) can be turned on smoothly, it is usually necessary to send several cycles of driving pulses continuously. In the hard-switching full bridge involved in this article, 2 driving pulses are actually sent to ensure that UCD3138 can successfully detect the correct input voltage.

1.2 Hardware Circuit Design

The hardware circuit to realize the Single Frame function is relatively simple, as shown in Figure 1. The VIN_CT network is connected to the center tap of the secondary side of the transformer, and then connected to the EAP2 pin of the UCD3138 after RC filtering. The main function of this circuit is to filter and scale the voltage at the center tap of the transformer.

Figure 1: Single Frame hardware circuit

The turns ratio of the transformer is 5:2:2. The relationship between the voltage at EAP2 and the input voltage is:

1.3 Software Design

The software design to realize the Single Frame function includes two parts: the configuration of the drive signal and the voltage acquisition and conversion. The first part is the core configuration. The following focuses on the first part.

1. Setting of switching cycle

The following code sets the switching period to 5us, i.e. 200KHz. The calculation formula is:

#define PERIOD (20000)

Dpwm0Regs.DPWMPRD.all = PERIOD;

2. Setting of single pulse length

The following code completes the setting of the single pulse width length, including the setting of the dead zone. The time width set by this code is. That is, two pulses with a pulse width of 651ns are output in one cycle.

Dpwm0Regs.DPWMEV1.all = 20;

Dpwm0Regs.DPWMEV2.all = 2625;

Dpwm0Regs.DPWMEV3.all = 20 + 10000;

Dpwm0Regs.DPWMEV4.all = 2625 + 10000;

3. Setting the sampling time

Considering that when the voltage at the center tap of the secondary side of the transformer becomes high voltage, it will be accompanied by spikes and oscillations. In order to prevent sampling errors, the sampling point setting needs to avoid the start time. The following code sets the sampling point position: close to the end time of the pulse, which is 600ns.

Dpwm0Regs.DPWMSAMPTRIG1.all = 2400;

1.4 Measured waveform

As shown in Figure 2 below, the green line is the full-bridge primary drive (i.e. single pulse) waveform, and its time length is about 650ns, which is consistent with the software design. The yellow line is the voltage waveform at the center tap of the transformer secondary side. The first wave head is because the full-bridge primary side is not fully turned on, causing the input voltage to not be fully transmitted to the secondary side, while the second pulse accurately reflects the input voltage information. At this time, the input voltage is 50V, and the platform of the yellow line is 20V, which is consistent with the theoretical calculation.

Figure 2: Single Frame measured waveform

2. Design and implementation of feedforward function

The feed forward function is an important feature of UCD3138. With the help of the hardware circuit that implements the Single Frame function, UCD3138 can know the current input voltage; when the input voltage changes drastically, the feed forward function can respond quickly and adjust the duty cycle to stabilize the output voltage as soon as possible.

2.1 Description of the implementation principle of the feedforward function

The output of the feedforward module inside the UCD3138 chip is a gain value, which will be multiplied by the output of the loop to jointly determine the duty cycle. The gain of the feedforward module output is determined by the formula: Gain = Kc + Kp×ΔV. Where:

◎Kc is a constant, usually set between 0.5 and 0.7, to facilitate the adjustment of the duty cycle in both directions;

◎Kp is the amplification factor of the input voltage difference. This value is nonlinear, that is, the greater the error, the greater the gain. When the error is small, this value is 0;

◎ΔV is the difference between the input voltage after the jump and the input voltage before the jump, that is, Vref(DAC)-Vin_sense. After the input voltage jumps, the value of Vref(DAC) will gradually approach the new input voltage to ensure that the value is equal to the latest current input voltage.

The schematic diagram of the feedforward processing module inside the UCD3138 chip is shown in Figure 3.

Figure 3: Feed-forward internal processing module

As shown in Figure 4, the output of the feedforward module is directly multiplied by the final output of the loop, and then the duty cycle is adjusted based on the multiplication result. This ensures that the feedforward result can quickly adjust the current duty cycle.

Figure 4: The feedforward output is ultimately multiplied by the loop output

2.2 Implementation of feedforward function

The hardware design of the feedforward function mainly includes the input voltage detection circuit, which has been described in Chapter 1 and will not be repeated here. The software design mainly includes the configuration of the Vref (DAC) value, the configuration of Kc and the enablement setting of the feedforward function.

1) Configuration of Vref (DAC) value

The following function implements the update of Vref(DAC) value according to the size of v_input_error. v_input_error is the difference between the currently acquired input voltage and the previously acquired input voltage. This function is included in a state machine and is executed once every 100us. It will be executed 300 times continuously to ensure that Vref(DAC) is approximately equal to the current input voltage before enabling the feedforward function.

if(v_input_error > 10)

{

if(FeCtrl2Regs.EADCDAC.bit.DAC_VALUE > 3000) //can not lower than 35V;

{FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = FeCtrl2Regs.EADCDAC.bit.DAC_VALUE - 1;}

}

else if(v_input_error < -10)

{

if(FeCtrl2Regs.EADCDAC.bit.DAC_VALUE < 14000) //can not higher than 80V;

{FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = FeCtrl2Regs.EADCDAC.bit.DAC_VALUE + 1; }

}

If the error is small, that is, the input voltage is stable, the system software prepares to turn on the feed-forward function and then enters the state machine for normal operation.

if ( abs(v_input_error) < 10) //Vin error is small

{

supply_state = STATE_REGULATED;

Filter0Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL =2;//Enable Feed Forward

}

2) Configuration of Kc value

When the input voltage is stable, if Kc is directly configured to a value between 0.5 and 0.7, enabling the feedforward function will affect the output of the normal loop and cause the output voltage to drop, as shown in Figure 5 below.

Figure 5: Improper Kc activation causes output drop

The reason for the drop is that the normal output of the loop is suddenly multiplied by Gain=Kc=0.5~0.7, so the duty cycle is immediately limited and the output voltage drops. The output voltage does not return to normal until the duty cycle is expanded to normal size after the loop has gone through multiple cycles.

Therefore, in practical applications, it is necessary to gradually reduce Kc from 1 to the required value (Kc is selected as 0.7 in the hard full-bridge software involved in this article). In addition, Filter2 is used in the actual design to achieve the setting of nonlinear gain and Kc, so the software configuration is as follows.

Uint32 filter2_kc;

int filter2_kc_step = 0x200;

inline void handle_regulated_state(void)

{

filter2_kc = Filter2Regs.FILTERPRESET.bit.PRESET_VALUE;// It is Kc

if(Filter2Regs.FILTERPRESET.bit.PRESET_VALUE > 0x5A0000)

{

Filter2Regs.FILTERPRESET.bit.PRESET_VALUE = filter2_kc - filter2_kc_step;

Filter2Regs.FILTERPRESET.bit.PRESET_EN = 1;

}

}

Among them, handle_regulated_state is a state in the software state machine, which is executed every 100us. Through such a loop function, it can be ensured that Kc is configured from 1 to 0.7 (0x5A0000/0x7FFFFF=0.7) in a step-by-step manner, preventing the output voltage from dropping.

3) Enabling the feedforward function

After the above perfect pre-configuration, the feedforward function can be enabled. After enabling, KC slowly decreases from 1. The startup setting is realized by the following code. The "OUTPUT_MULT_SEL" bit is used to select the value multiplied by the loop output to determine the final duty cycle. When set to 2, the output of the selected feedforward is multiplied by the loop output, that is, the feedforward is enabled.

Filter0Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL =2;

References

【1】 UCD3138 datasheet, Texas Instruments Inc., 2011

【2】 UCD31xx Central Interrupt Module (CIM) Programmer's Manual, Texas Instruments Inc., 2011

【3】 UCD31xx Fusion Digital Power Peripherals Programmer's Manual, Texas Instruments Inc., 2011

【4】 UCD31xx Miscellaneous Analog Control _MAC_, Texas Instruments Inc., 2011