Current Design Tips: Estimating Temperature Rise of Surface Mount Semiconductors

Estimating semiconductor temperature rise used to be simple. You simply calculated the power dissipation of the component and then used an electrical simulation of the cooling circuit to determine the type of heat sink required. The desire to eliminate heat sinks for size and cost reasons complicates the issue. Semiconductors mounted in thermally enhanced packages require the board to act as a heat sink and provide all the necessary cooling. As shown in Figure 1, heat flows into the printed wiring board (PWB) through a metal mount and the package. The heat then flows laterally through the PWB traces and dissipates through the board surface to the surrounding environment by natural convection. The important factors affecting the temperature rise of the die are the copper content in the PWB and the surface area available for convective heat transfer.

Figure 1 Heat flows laterally through the PWB traces and then dissipates from the PWB surface to the surrounding environment.

Semiconductor data sheets usually list the thermal resistance from junction to ambient for a certain PWB structure. This means that the designer can simply multiply this thermal resistance by the power dissipation to calculate the temperature rise. However, if the design does not have a specific structure, or if the thermal resistance needs to be further reduced, many problems will arise.

Figure 2 shows a simplified electrical simulation of the heat flow problem that allows us to analyze further. The IC power supply is represented by a current source, while the thermal resistance is represented by a resistor. Solving this circuit at various voltages provides a simulation of the temperature. There is a thermal resistance from the junction to the mounting surface, while the lateral resistance throughout the board and the resistance from the board surface to the ambient together form a ladder network. This model assumes 1) the board is mounted vertically, 2) there is no forced convection or radiation cooling, and all heat flow occurs in the copper of the board, and 3) there is almost no temperature difference between the two sides of the board.

Figure 2 Electrical equivalence of heat flow simplifies temperature rise estimation

Figure 3 shows the effect of increasing the copper content in the PWB on improving thermal resistance. By increasing the 1.4 mils copper (double-sided, half an ounce) to 8.4 mils (4 layers, 1.5 ounces), it is possible to increase thermal resistance by a factor of 3. The two curves in the figure are: one for a small package with a 0.2-inch diameter heat flow into the board; the other for a large package with a 0.4-inch diameter heat flow into the board. Both curves are for a 9-inch square PWB. Both curves are closely related to the nominal data and both are helpful in estimating the effect of changing the datasheet board structure. However, this data needs to be used with caution, as it assumes that there is no other power dissipation in the 9-inch square PWB, which is not the case.

Figure 3 Electrical equivalence of heat flow simplifies temperature rise estimation