Inverting level conversion circuit with negative potential

Publisher:MysticMoonLatest update time:2012-10-11 Source: 21IC Reading articles on mobile phones Scan QR code
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Digital system design requires consideration of multiple core voltages. Memories operate at 1.8V, I2C and FPGA devices operate at 3.3V, microcontrollers operate at 5V, and CCD image sensors require -9V to 8V. The clock for each device must be adapted to its operating voltage.

The level conversion circuit in the figure below can be used to adjust the input clock signal to the appropriate logic high and logic low levels, including negative voltages. This feature is
very convenient for devices that require negative voltages, such as charge-coupled device sensors. Although the output clock of the circuit will be 180° inverted relative to the input clock, this inversion does not affect the function of the device.

This is a simple and fast level shifting circuit that can adjust the input clock to positive and negative voltage levels.

The level shifting circuit includes fast switching transistors Q1 and Q2. The user selects the level shift high and low, which are DC bias voltages connected to the emitters of the transistors to match the required output high and low logic levels. C1, R1, D1, C2, R2, and D2 keep the base voltage of Q1 and Q2 close to the emitter voltage.

Since memory and CCD sensors usually have high-frequency clocks, the passage of low-frequency noise can be prevented by selecting C1 and C2. The circuit in the figure uses a 20MHz signal for measurement (below), so the values ​​of C1 and C2 are both 100pF. When the input voltage clock is low, Q1 is turned on and Q2 is turned off, driving the output voltage clock to a high potential for level shifting. When the input voltage clock is high, Q1 is turned off and Q2 is turned on, driving the output voltage clock to a low potential for level shifting, even if the potential is negative relative to ground.


Since the circuit has a high switching speed, the component leads should be as short as possible to reduce inductance, especially the connection between C3 to C6 and the emitter of each corresponding transistor, and the connection to the ground layer or output ground return.

Reference address:Inverting level conversion circuit with negative potential

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