Design of LCD display driver IP based on NioslI

introduction

The NioslI embedded processor is a SOPC solution proposed by Altera. It is a 32-bit embedded processor that users can configure and build at will. Combined with rich peripherals, it can quickly and flexibly build a powerful SOPC system. Altera provides some general IP cores, allowing users to easily integrate their own special functions; but for some specific peripherals, there are no ready-made IP cores, such as the LCD module CBGl28064.

Users can add custom IP cores to SOPC designs by using custom logic. In practical applications, LCD displays are widely used in intelligent instruments, meters, and low-power electronic products due to their low power consumption, small size, thinness, and simple control and drive. This article takes the LCD display module CBGl28064 of Shenzhen Akita Shijia Industrial Co., Ltd. as an example, designs an LCD display driver IP core in a NioslI-based SOPC system, and downloads it to the Cyclone series FPGA to realize the display driver of the LCD.

1 CBGl28064 LCD display module

CBG128064 is a liquid crystal module with two HD61202 as column drivers and one HD61203 as row driver. HD61202 is a graphic liquid crystal display controller with drive output, which can be directly connected to an 8-bit microprocessor; while HD61203 only needs to provide power to generate row drive signals and various synchronization signals. The CBGl28064 liquid crystal display module has a built-in display memory RAM, and the display status of each pixel on the display screen corresponds to each bit of data in the display memory RAM. The data in the display memory is directly used as the driving signal for graphic display. The external processor only needs to set the required display mode through its 8-bit data line and 6 control lines, and other functions are automatically completed by the module. HD61202 provides 7 simple instructions: display on/off instruction, display start row (ROW) setting instruction, page (RAGE) setting instruction, column address (Y Address) setting instruction, read status instruction, write data instruction, and read data instruction.

2 Solution Selection

There are usually two ways to implement NiosII embedded processor to drive LCD display:

One is to use the existing parallel input/output (PIO) core. This core provides a memory mapping interface between the Avalon bus from the controller port to the general I/O port, connecting the interface of the LCD module to the parallel port of the NiosII embedded processor. The NiosII embedded processor controls the LCD module by operating its port. This method is similar to the operation of a single-chip microcomputer, with simple timing and easy implementation; however, in the SOPC system, the hardware needs to design the I/O port connected to the peripheral, and the software needs to write an interface program for read and write control, which increases the processor's time overhead and does not give full play to the parallel processing capabilities of the FPGA.

The other is to use a custom IP core. The LCD module is regarded as an external memory or I/O device, and is connected to the Avalon bus of the NiosII embedded processor as a slave device. The processor controls it by accessing the I/O device or reading and writing the memory. This method requires writing an HDL module, defining the control, status, data registers and control bits by yourself, and can flexibly implement complex timing control. Once the design is completed, it can be packaged as an independent component available in SOPC BLdldel. Users can use it like other peripherals provided by Altera, and it can be provided to other designers. This article uses this method to implement it.

3 LCD display driver design

Figure 1 is a system structure diagram. The design focuses on the design of the LCD display driver module. According to the modular and hierarchical design concept, the display driver can be implemented in three parts, namely the task logic part, the register file part and the Avalon bus interface part. The task logic part describes the read and write logic functions of the LCD module; the register file part provides a channel for accessing the internal registers; the Avalon bus interface part operates the registers through the top-level interface module, thereby realizing access and control of the behavior module. Among them, DATA[70] is an 8-bit data line, CS1 and CS2 are chip select signals, RS is the instruction/data selection signal, R/W is the read/write selection signal, RST is the reset signal, and E is the read/write enable signal.

3.1 Task Logic

Task logic is the core part of the entire driver. To achieve LCD display control, it is necessary to design it according to the specifications and timing requirements of the CBG128064 driver controller. In the sequential logic circuit, the coordination of data signals and control signals is relatively complex, but very important. Using finite state machines can easily design complex digital circuit systems.

This paper uses finite state machine to realize the core logic of display driver. According to the read and write commands and read and write timing requirements of the driver controller, this paper designs three state machines, namely read and write control state machine, read and write state machine and read and write timing state machine.

As shown in FIG. 2 , the read/write control state machine is used to perform busy state detection and read/write operation control when a read/write request occurs, and to provide a timing state machine read/write signal in each state.

As shown in Figure 3, the read/write state machine gives a read or write signal and completes the state transition between write command, write data and read data under the control of the read/write control state machine. In each state, LCD display data and control signals such as chip select, written data/instructions, etc. are given.

As shown in Figure 4, the read/write timing state machine is used to control the moment of reading or writing peripherals, and gives a read/write completion signal when the read/write is completed. Among them, the read/write signal is given by the read/write operation in Figure 2. According to the read/write timing requirements of CBGl28064, when R/W is high, the data in the display RAM is read; when R/W is low and at the falling edge of E, the data is written to the display RAM. The read/write signals of the read/write timing state machine are given by the read/write control state machine, where E is the module enable signal.

3.2 Register Group

The register group consists of a series of registers that provide software with access to the hardware. The registers in the register group are set according to the specific logical functions that need to be implemented in the task logic, and the data in the task logic is transmitted through these registers. In this design, the register group sets an 8-bit page address register, an 8-bit column address register, and a 32-bit data register.

3.3 Ayalon Bus Interface

The Avalon bus interface of the display driver requires a simple Slave port. This port uses fewer Avalon signals to handle simple register read/write transfers. This module is a top-level module that interfaces with the Avalon bus. Its main function is to instantiate and encapsulate the task logic module and the register module so that its signal type conforms to the Avalon bus signal specification and the signal specification of the external module. The top-level interface is defined as follows:

3.4 Display driver packaging and software design

Directly add the designed display driver IP Core and Verilog HDL language description files in SOPC Builder, and set the relevant signal lines and transmission parameters according to the Avalon bus transmission specification. Since the user program is directly written in the NiosII IDE environment, there is no need to write a driver. After completion, add the display driver IP Core to the SOPC project, compile, and download to the FPGA device.

In the NiosII IDE environment, you can write programs using modules you add yourself, and directly call IOWR (BASE, OFFSET, DATA) and IORD (BASE, OFFSET) to read and write internal registers. This article uses a structure to define a structure pointer pointing to a module to read and write registers.

CBGl28064 itself does not have a font library. There are two ways to add a font library: one is to put the required font library into the hardware ROM, which increases the hardware resource cost and lacks flexibility; the other is to define the font library in the software and display it by writing data registers. This design adopts the second method, defining the font library in the software, and writing a simple display test program to display the words "ZHONG GUO" on the LCD screen. The test results show that the design is correct and feasible. In addition, the graphic data generated by the font software can also be used for graphic display.

Conclusion

This paper uses finite state machine to design the CBGl28064 LCD module driver hardware logic, and encapsulates the display driver IP core to form a modular independent component, so that it can be reused in other projects; on this basis, a user-customized system-on-chip is built based on the NiosII embedded processor. After testing on the Cyclone series FPGA, the driver can display characters and graphics on the C-BGl28064 LCD module. The entire system reflects the flexibility and scalability of the SOPC embedded system.

References:

[1]. HD61202 datasheet http://www.dzsc.com/datasheet/HD61202_1078805.html.
[2]. HD61203 datasheet http://www.dzsc.com/datasheet/HD61203_1078817.html.
[3]. ROM datasheet http://www.dzsc.com/datasheet/ROM_1188413.html.