MSP430 communication resources IIC communication

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MSP430 communication resources IIC communication [Copy link]

1. I I C Description

The above figure shows that there should be at least one microcontroller in the IIC bus topology. The controller communicates with other associated devices through the SCL and SDA lines of the IIC bus. Based on the traditional serial bus communication mechanism, IIC bus communication is also achieved through the cooperation of SDA and SCL, and the transmission rate includes three categories: standard (100kps), fast (400kps), and high-speed (3.4Mbps).

2. IIC bus timing

Startup timing: When SCL is high, the falling edge of SDA indicates start.

Stop timing: When SCL is high, the rising edge of SDA indicates stop.

※From this, we can see that data transmission should occur when SCL is at a low level, and not during a high level. Further, we can see that the SDA level is read when SCL is at a high level.

The content of the data frame includes the start and stop signals, the 7-bit or 10-bit slave address, the transmission direction flag, the data bit (8 bits), an ACK bit (acknowledgement signal) after each byte of data, and then the end signal to end the data frame. In general, it is "start--address (7 or 10 bits)--R/W--data--ACK--data--ACK--....--stop"

3. I2C circuit structure diagram

The data sheet describes that the USCI module is in reset state after PUC or manual setting of the UCSWRST bit. If it is to work in I2C state, UCMODEx should be set to 11. After setting, just clear the UCSWRST bit to make the USCI work.

4. Some main configuration statements of IIC

UCB0CTL1 |= UCSWRST; //Enable software reset, first turn off USCI_B0 mode for initialization //settings

UCB0CTL0 = UCMST + UCMODE_3 +UCSYNC; //I2C master, synchronous mode

UCB0BR0 = 12; //12 division

UCB0BR1 = 0;

UCB0I2CSA = 0x4e; //Set slave mode

UCB0CTL1 &= ~UCSWRST; // Clear software reset