Design of multifunctional network electric energy meter based on AD73360

This article introduces the overall system design of a multifunctional network energy meter based on the AD73360 chip. The FPGA is connected to the AD73360 chip, and the FPGA writes control words to the AD73360 chip, and then processes the collected data. The hardware design of the multifunctional network energy meter based on AD73360 is introduced in detail, and the VHDL design of FPGA is also introduced. This design has the functions of power parameter monitoring, power quality analysis, time-divided power metering, fault recording and network remote meter reading.

This design is a multifunctional network energy meter based on the AD73360 chip of ADI. Traditional multifunctional energy meters usually use dedicated energy metering ICs for measurement or use AD chips to sample data at the front end, and then use DSP or MCU to process the data. If a dedicated energy metering IC is used, an additional processor is required to control the meter, which increases the cost of the meter; if the second solution is used, the real-time processing capability of the meter will be affected due to the cost and processing power of DSP or MCU. For the above reasons, in this design, the AD73360 chip is used at the front end to sample the voltage and current, and the FPGA is used at the back end to process the collected data and control the meter as a whole. Since FPGA uses a pure hardware working mode, it has strong real-time performance; at the same time, due to the powerful processing power of FPGA, one FPGA can be used to complete all data processing and control work. This can simplify the hardware design and reduce costs.

AD73360 is a 6-channel analog front-end processor from Analog Devices, which is particularly suitable for energy metering [1]. The chip has 6 16-bit A/D conversion channels, each of which can be sampled synchronously, while ensuring a signal-to-noise ratio of 77 dB from DC signals to 4 kHz signal bandwidth. Each channel also has an independent programmable input amplifier (PGA) with an adjustable gain from 0 to 38 dB. The chip can be set to provide four sampling frequencies, namely 64 kHz, 32 kHz, 16 kHz, and 8 kHz (obtained by dividing the 16.384 kHz master clock).

1 Multifunctional Electric Energy Meter System Design

The multifunctional network energy meter (hereinafter referred to as the energy meter) consists of data acquisition, control and processing, power supply, network interface, display, storage and calendar clock, as shown in Figure 1. The data acquisition part is composed of precision small mutual inductor, signal conditioning circuit and AD73360 chip. The control and processing part uses Altera's FPGA chip Cyclone II 2C35F484C8. The power module provides power for the entire energy meter system, with a total of 2 DC power outputs, one for the data acquisition board and one for the energy metering SoPC chip. Considering the electromagnetic compatibility test, the power system is required to suppress high-frequency pulse interference and automatically protect against overvoltage. The network interface part uses DMA9000A network chip and uses RJ-45 interface. This system supports Ethernet protocol. The display part uses high-quality LCD display module, and each screen can display 8×4 Chinese characters (16×16) or 128×64 pixel graphics. The storage module uses IIC bus to communicate with an E2PROM for data freezing. The calendar clock uses a dedicated calendar clock chip to provide date information for the system. Table 1 shows the specific functions and design indicators of the meter [2].

2 Electricity Meter Hardware Design

2.1 Data acquisition module hardware design[2]

As can be seen from Figure 1, the data acquisition module consists of three parts: mutual inductor, signal conditioning circuit and AD chip. The three-phase voltage signal of this system adopts single-ended input mode, and the three-phase current signal adopts differential input mode. Since this system uses 3.3 V to power the AD73360 chip, the input current is set at 10 mA and the input voltage is set at about 700 mV.

2.1.1 Current input circuit design

The current input uses a dedicated current transformer to reduce the input current to about 10 mA. This system uses the YWH type electric energy meter dedicated transformer produced by Harbin Sanjiangda Electric Power Technology Co., Ltd. The YWH series transformer is a branch product of the miniature transformer. It is a new generation of miniature precision current transformer designed for wide-range electronic electric energy meters. It has a wide working current range (can be overloaded 4 to 10 times), good error linearity (ratio error less than 0.01%, angle error less than 0.3'), flame-retardant ABS plastic shell, epoxy resin encapsulation, high insulation strength, beautiful appearance, and a variety of specifications for users to choose from to meet different installation needs. This design uses the YWH-1 type, whose current ratio is 1.5 (6) A/5 (20) mA, secondary load resistance is 5 to 20 Ω, and accuracy is 0.1.

2.1.2 Voltage input circuit design

The three voltage signals are directly reduced from 220 V to about 700 mV through a resistor network. Each voltage signal input circuit consists of five 204 resistors and one 332 resistor to ensure that the 220 V mains power is reduced to about 700 mV input to meet the needs of AD73360.

2.1.3 Signal conditioning circuit design

Since the voltage and current signals of this system use different input methods, different signal conditioning circuits are required. The voltage conditioning circuit uses an RC circuit to form an anti-aliasing filter, while ensuring that the signal frequency of the input AD is less than 0.5 times the AD sampling rate.

2.1.4 AD73360 Circuit Design

VINP1-6 and VINN1-6 are signal input pins; MCLK is connected to the system master clock. Since AD73360 was designed with simple interface with DSP in mind [1], SCLK, SDO, SE, SDI, SDIFS, and SDOFS can be directly connected to the FPGA I/O port during design.

2.2 Control and data processing module[3]

The control and data processing of this system uses the FPGA chip of Altera, Cyclone II 2C35F484C8. In order to simplify the hardware design difficulty of this system, the finished FPGA development board is directly used. In this way, only the peripheral calendar clock chip, LCD and network interface circuit need to be designed.

3 Control and data processing programming[4]

This system uses FPGA and Altera's NIOS II soft core to control the system and process the collected data[5]. Finally, the μC/OS II operating system is used to integrate the entire system. The design is divided into two parts: one is the control part, which includes the control of AD chips, network interfaces and other modules; the other is the data processing part, which is mainly responsible for processing the data collected by AD73360.

3.1 CPU Design

The chip includes AD controller, FIFO, energy metering, configuration register, NIOS II soft-core microprocessor, calendar clock interface, digital frequency converter DFC (Digital to Frequency Converter), IIC interface and LCD controller, etc. Its structure is shown in Figure 2.

Among them, the input of the AD controller is the three-phase voltage and three-phase current (serial data of 6 channels) collected on the signal acquisition board. The AD controller converts the serial data of the 6 channels into parallel data and stores it in the corresponding FIFO according to the timing of the 16-bit ∑-△A/D chip AD73360 of ADI Company of the United States; the 6-channel FIFO saves the AD data of 6 channels and 1 cycle sent by the AD controller for subsequent calculation. Another advantage of this is that the electric energy metering module can realize the pipeline structure and speed up the calculation speed; the electric energy metering module mainly uses FPGA to realize the measurement of active, reactive and apparent power of electric energy. The configuration register saves configuration data, historical power data, frozen data, etc.; the NIOS II soft-core microprocessor completes the scheduling of the entire electric energy metering chip; the calendar clock interface is connected to the external calendar clock chip to provide clock information for the chip for use by the NIOS II soft-core microprocessor, thereby forming a multi-rate electric energy meter. The calendar clock chip uses the trickle charging time chip DS1302 from Dallas, USA; DFC conversion is to convert the measured electric energy value into the number of pulses for output, so as to calibrate the meter; the IIC interface controls the external IIC read-only memory AT24C256, which is a two-wire serial electrically erasable programmable read-only memory from ATMEL, USA; the LCD controller realizes the driving function of the external LCD.

3.2 AD control design

The AD interface module completes the initialization of AD73360 (setting the frequency division coefficient, AD sampling rate, programmable gain, and working mode), reads the output data, and completes the serial/parallel conversion. In this design, the main frequency of the FPGA is 50 MHz. It is found through experiments that the maximum working frequency of the AD SCLK is 2.048 MHz, so that the FPGA can ensure the accurate acquisition of the SCLK signal.