Research on the design of LED large screen control circuit

LED dot matrix is ​​an important display terminal for public information, among which large-screen LED dot matrix display screens are used in many occasions. Large-screen display technology is more difficult than small and medium-sized screen display because the screen is large, the number of LED dots is large, and each dot must be refreshed in a very short time, which requires its scanning rate to be very high. In addition, as an important medium for information release, large screens have high requirements for stability, reliability and scalability. Only a well-designed control circuit can meet the above requirements. This article focuses on several design methods of control circuits in LED large screen design, and provides different solutions for different design requirements.

1The working principle of LED large screen system

A typical LED large-screen display system is mainly composed of a signal control system, scanning and driving circuits, and an LED array. The system structure is shown in Figure 1. At present, the screen design of most LED displays adopts a modular structure. Its basic unit is the LED display unit module. The screen size and shape can be flexibly changed, and the installation and maintenance of the display are also very convenient.

Figure 1 System block diagram

The signal control system is a microcomputer system, a single-chip microcomputer system, a microcomputer-single-chip microcomputer master-slave control system, a programmable logic device control system, an infrared remote control system, a paging reception and control system, etc. The task of the signal control system is to generate or receive the digital signal required for the LED display, and control the various components of the entire LED display system to work in a certain division of labor and timing coordination. The row drive circuit is mostly a triode array, which provides a large current to the LED. The column drive is composed of a serial input and parallel output shift register and a latch (or a shift register with a latch function).

When the display data is ready, the control system first sends the first row of data to the shift register and latches it, and then the row scanning circuit selects the first row of the LED array, lights it up for a period of time, and then displays the subsequent rows in the same way until a frame of display content is completed, and so on. According to the principle of visual persistence, a display of 24f/s can be achieved so that the naked eye has no obvious sense of pause, which is equivalent to a response time of less than 40ms. When the area of ​​the LED display is large, the amount of data transmitted is also very large, which increases the response time of the display system and causes flicker. In order to improve the visual effect, it can be displayed in parallel in partitions.

During high-speed dynamic display, the brightness of the LED is proportional to the light-emitting time within the scanning cycle, so grayscale display can be achieved by modulating the ratio of the LED light-emitting time to the scanning cycle (i.e., duty cycle).

2LED large screen control circuit design

The design of control circuit is the core of large screen system design. Control circuit design includes signal control system, scanning circuit and driving circuit design. Control circuit design is generally composed of data storage, data buffer, counter, synchronous controller, read-write controller, master-slave controller, address controller, frame memory, data selector, grayscale modulator, shift register, etc. At present, LED display control circuit design widely uses two types of devices as its control core, one is single chip control system, the other is programmable logic device.

2.1 Control circuit design based on single chip microcomputer

There are two main schemes for control circuits based on single-chip microcomputers. One is to use a single-chip microcomputer as the main control device to control and coordinate the display of the entire display system of the large screen. The other is to use multiple single-chip microcomputers to form a multi-processor, one of which is used as the main CPU and the others are used as sub-CPUs to control the display of the large screen together.

Figure 2 is a schematic diagram of the control circuit structure designed with a single-chip CPU, using the 89C52 single-chip microcomputer as the control core. The single-chip microcomputer receives display data sent from a PC or other information source, stores it in Flash, and uses RAM6264 as a field display buffer to achieve different display broadcasting modes. 89C52 controls the switching switches C1, C3 and C2, C4 to read and write data to frame memories A and B alternately at the same time, and converts the read data into parallel 5 serial data and sends it to the display screen for display refresh. Among them, the automatic address generator is composed of 4 counters in series, and is equipped with an oscillation circuit to provide a counting clock. For a monochrome screen with M×N pixels, when the refresh frequency is 60Hz, the counting frequency is M×N×60Hz. For a large multi-grayscale color screen, grayscale modulation must be performed before the data is sent to the display screen to reproduce the color of the image, which requires a higher data processing speed. The use of a single-chip microcomputer control may not meet the speed requirements.

Figure 2 Schematic diagram of the single-chip CPU control circuit structure

Since many single-chip microcomputers have I/O ports with a driving capacity of more than 15mA and are relatively cheap, multi-processor solutions are also used in the design of large screens. The basic characteristics of the system are: there are multiple processors in a display group, including a main CPU and multiple sub-CPUs, and its structural diagram is shown in Figure 3. The task of the main CPU is to obtain display information through data acquisition or communication with the outside world, and then transmit it to the sub-CPU. The main CPU is also responsible for row scanning and sending display synchronization information. The sub-CPU receives the data information of the main CPU and stores it in the internal RAM. Then, according to the control information sent by the main CPU, the appropriate column output port is selected for column scanning. Assuming that the maximum number of pins that can be used as output ports of each sub-CPU is m, and the number of columns of each LED matrix is ​​n, the maximum number of LED blocks that can be driven by each chip is m/n. In this way, each single-chip microcomputer is responsible for one or several LED blocks, which is flexible and easy to expand. At the same time, it reduces the burden of the main CPU and increases the refresh frequency of the dot matrix.

Figure 3 Schematic diagram of multi-CPU control circuit structure

This solution is ideal for large-screen designs with multiple displays. Separate sub-CPUs are used to perform column scans on different display screens, and then unified row scans are performed through the main CPU. Although the control circuit uses more components, the circuit structure is simple and easy to implement.

2.2 Control circuit design based on CPLD/FPGA

The frequency of the image signal is high: the data volume is large, and real-time processing is required. In addition, the digital logic of the LED large screen circuit is quite complex. The use of CPLD/FPGA to design the control circuit can simplify the system structure and facilitate debugging. Figure 4 is the schematic diagram of the CPLD/FPGA design control circuit. The CPLD/FPGA device is used to integrate a large number of circuits such as synchronous control, master-slave control, read-write control and grayscale modulation, making the image data processing faster, the image more stable, and the system structure compact, and the working reliability is improved.

Figure 4 CPLD/FPGA control circuit schematic

Other functional modules outside the dotted line in Figure 4 are all implemented by CPLD/FPGA programming, replacing the complex hardware circuit design with software programming. Compared with the single-chip microcomputer control circuit in Figure 2, the circuit structure is obviously simpler, the circuit area is reduced, the reliability is enhanced, and the debugging is also simpler. Since CPLD/FPGA can process multiple processes in parallel, it is more efficient than the sequential processing of tasks by single-chip microcomputers, and the refresh frequency of the dot matrix is ​​also increased.

In addition, the on-chip resources of programmable logic devices are becoming more and more abundant. Many devices have integrated RAM blocks. For example, the cost-effective FPGA Hurricane EP1C6 launched by Altera has 20 RAM modules integrated inside, each with a capacity of 4Kbit. These RAM blocks can be set to single-port RAM, dual-port RAM, FIFO, etc. through software to meet the system's needs for data processing. For example, when designing a grayscale modulator, the higher the grayscale level of color reproduction, the higher the data processing speed while maintaining the same refresh frequency. At this time, the internal RAM block of the FPGA can be set to a dual-port RAM. As a buffer for grayscale modulation, while reading the data in the frame memory, the data read last time is gray-scale modulated. The two are performed alternately, which speeds up the data processing rate. In the large-screen design with high requirements for display system integration and stability and more image grayscale levels, it is more convenient to design control circuits using programmable logic devices.

Some other control circuit design schemes use a combination of single-chip microcomputer technology and EDA technology, using single-chip microcomputers to implement data processing, storage and communication functions, and CPLD/FPGA to implement data grayscale modulation, scanning display and other functions. This scheme does not require very high resources for single-chip microcomputers and CPLD/FPGA, and the circuit design is relatively easy, which not only ensures the display effect, but also saves design costs.

2.3 Application of embedded systems in large screen design

Because embedded computer technology has advantages that single-chip microcomputers cannot match: the instruction execution speed is one order of magnitude higher than that of ordinary single-chip microcomputers, and it supports large-capacity storage space: a wide range of memory interface types, high-bit width data bus, and multiple peripheral communication interfaces. In particular, the use of embedded operating systems can more effectively manage the allocation of system resources. Through its efficient scheduling algorithm, the design of the entire application can be implemented in a multi-tasking manner, greatly improving the operating speed and reliability of the system. The control circuit design of the Linux-based embedded system is shown in Figure 5.

Figure 5 Schematic diagram of the control circuit of the embedded system based on Linux

2.4 Driving scheme for large screen display

There are three main driving schemes for LED large screens: serial control driving mode, parallel control driving mode, and application of highly integrated dedicated chip driving. The serial control driving mode is to send the displayed data to the dot matrix driving circuit in serial mode. Its characteristics are simple line connection, convenient debugging, and high unit reliability. The chips that can be used for the serial control driving mode are: MC4094, 74LS595, 9094, etc. The row drive requires a large power and is generally driven by a high-power transistor. The row scan can be controlled by a three-to-eight decoder, etc. Since the serial input and parallel output chips can be cascaded, it provides support for the cascade of LED units.

The parallel control drive mode sends the displayed data to the point drive circuit in parallel, and its advantage is that the data refresh rate is fast. For the parallel drive mode, latch chips such as 74LS374 can be selected, and the control and drive are formed together in a head-to-tail manner. The parallel drive solution is easy to control and has low system investment cost. Highly integrated dedicated driver chips such as ZQL9701 integrate row and column control and some peripheral drive circuits, making the unit control and drive simpler and the system stability more reliable. The use of ZQL9701 will make the system display grayscale reach 256 levels, but the system cost is relatively high. For small and medium-sized production and applications, the first two drive solutions should be used as the main ones. For large-scale production and applications with higher requirements, dedicated integrated chip drivers can be selected.

3 Conclusion

The design schemes of LED large-screen control circuits have their own characteristics. Different design schemes can be selected according to needs in actual engineering applications. When designing large screens with monochrome and low grayscale levels, a design scheme based on a single-chip microcomputer can be adopted. To achieve high-difficulty dynamic graphic special effects display and multi-grayscale display, a design scheme based on programmable logic devices or a design scheme based on embedded technology should be selected.