Incorporating PFC into Power Supply Design

Before the latest IEC61000-3-2 standard went into effect in 2005, most PC, monitor, and TV power supplies generated excessive power line harmonics when powered from single-phase 110 to 120V, 60Hz AC. Driven by this newer, more stringent IEC standard, power supply manufacturers began to minimize power line harmonics by adding power factor correction (PFC).

To understand the impact of IEC61000-3-2, it is best to first understand the ideal case of a load resistor (R) placed directly across the power line (Figure 1). In this case, the sinusoidal line current IAC is proportional to the line voltage VAC and in phase with that voltage. Therefore:



Figure 1

This means that for the most efficient distortion-free power line operation, all loads should behave as effective resistors (R), and the power consumed and delivered is the product of the RMS line voltage and line current.

However, many electronic systems have loads that require AC-to-DC conversion. In this case, the load on the power line of a typical power supply consists of a bridge diode driving a capacitor (Figure 2). It is a nonlinear load on the power line because both diodes of this bridge rectifier are in the direct power path during either the positive or negative half-cycle of the input AC power line voltage. This nonlinear load draws power line current only during the peaks of the sinusoidal power line voltage, which produces "multi-peak" input power line currents, which cause power line harmonics (Figure 3).


Figure 2Figure


3Nonlinear

loads make the magnitude of harmonics comparable to the fundamental harmonic current at line frequency. Figure 4 shows the magnitude of higher-order harmonic currents normalized to the magnitude of the fundamental harmonic at line frequency. However, only the harmonic currents given in Figure 1 that are at the same frequency as the line frequency and in phase with the power line voltage (in this case, the fundamental harmonic at line frequency) contribute to the average power delivered to the load. These harmonic currents affect the operation of other equipment on the same power line.


Figure 4The

magnitude of power line harmonics depends on the power factor of the power supply, which can vary from 0 to 1. Lower power factor values ​​produce larger harmonics, and higher power factor values ​​produce smaller harmonics. Power factor (PF) is defined as follows:


Where P = real power in watts; IRMS = RMS line current; VRMS = RMS line voltage; VRMS * IRMS = apparent power in volt-amperes/VA.

PF is also equal to the cosine of the phase angle (θ) between the line current and voltage; from this perspective, Equation 2 can be rewritten as follows:



The value of cosθ is a number between 0 and 1.

If θ = 0°, then cosθ = 1 and P = IRMS * VRMS, which is the same as the case of a resistive load. When PF is 1, the load consumes all the energy provided by the source.

If θ = 90°, then cosθ = 0; therefore, the power received by the load is zero. The generator that provides the power must provide IRMS * VRMS of power (even if no power is used to do useful work).

Therefore, for the diode bridge capacitor case in Figure 2, the only variable left in the PF definition of Equation 2 is the line current IRMS, because the line voltage (VRMS) is fixed to 120V by the power line generator. The higher the IRMs drawn by the power line for a given average power delivered to the load, the lower the power factor (PF). The AC-DC converter in Figure 2, which is powered by a 120-V ac power line voltage and delivers 600 W to the load while drawing 10 A of line current, has a PF = 0.5. However, the resistive load in Figure 1, which has a PF of 1, only draws 5 A from the power line (the load draws 600 W from the 120-V ac power line).
The power company loses money with low-PF loads because it must provide more generation capacity to meet the higher line current required due to the load's low PF. However, the power company only charges the customer for the average power delivered (in watts)—not for the volt-amperes produced.

This difference between volt-amperes and watts either appears as heat or, conversely, on the ac power line. The most common way to correct this is to use power factor correction. The IEC-61000-3-2 standard

for power factor correction

defines the maximum harmonic current allowed for a given power level. The original 1995 and 2001 versions of the standard were updated by version 3 in 2005 (see table). The 2005 version 3 imposed more stringent requirements on power line harmonic currents for (Class D) PCs, monitors, and TVs that consume between 75 and 600 W per phase and 16 A or less. To meet these requirements, designers must employ active power factor correction (PFC) in Class D power supplies.

Many PFC circuits employ a boost converter. A limiting factor in a conventional PFC boost converter is that it can only be powered by a rectified AC power line, which involves two stages of power processing (Figure 5). The waveforms produced by the converter better illustrate this problem (Figure 6). In addition, there is no simple and effective way to introduce isolation in a conventional boost converter.


Figure 5


Figure 6

Using a full-bridge expansion of the boost converter (which is then controlled as a PFC converter) is one way to introduce isolation (Figure 7). However, this approach adds complexity by adding four transistors in the primary and four diode rectifiers in the secondary (both transistors and rectifiers operate at a switching frequency of 100kHz). In addition, the four additional diodes are located in the input bridge rectifier operating at a line frequency of 50/60Hz.


Figure 7: Full-bridge extension of a boost converter controlled by a PFC controller provides isolation.

In addition to the low-frequency sinusoidal current, the line current will also be superimposed with the input inductor ripple current at a high switching frequency, which needs to be filtered by an additional high-frequency filter on the AC power line. The addition of 12 switches operating in hard-switching mode results in higher conduction and switching losses. The maximum efficiency of this two-stage approach and auxiliary switching devices is reported to be 87%.

This approach also has startup issues due to the impact of the boost DC conversion gain. It requires additional circuitry to pre-charge the output capacitor so that the converter can start.

To achieve 1kW or more, designers often use a three-stage approach (Figure 8). In Figure 8, the standard boost PFC converter and the isolated buck converter are located after the input bridge rectifier. This requires a total of 14 switches. At least six of the switches are high-voltage switches, which further reduces efficiency and increases cost. Still, with the best switching devices, the maximum efficiency can reach about 90%, which is still higher than the efficiency of the two-stage approach.


Figure 8: Power supplies of at least 1kW generally use a three-stage PFC converter.

For low and medium powers, there is an alternative approach that reduces the number of switches by using a forward converter as the isolation stage (Figure 9). Before taking this approach, it is important to note that although there are now 10 switches, the four switching devices in the forward converter impose greater voltage stress on the primary and secondary switches than the full-bridge solution. In addition, the full-bridge solution requires four magnetic components.


Figure 9: This PFC circuit uses an isolated forward converter, a setup that is generally reserved for low and medium power applications.
Bridgeless PFC converter

Dr. Slobodan Cuk, president of Teslaco, has broken new ground in this area by developing a patent-pending bridgeless PFC converter that is powered directly from the AC power line. This converter is claimed to be the first true single-stage bridgeless AC-DC PFC converter.

To achieve this feat, Cuk used a new approach to switching power conversion, which he called “hybrid-switching.” This approach uses a converter topology that contains only three switches: a controllable switch S and two passive rectifier switches (CR1 and CR2) (Figure 10). The two rectifiers are turned on and off according to the state of the main switch (S) when the input AC voltage is positive or negative. The topology consists of an inductor in series with the input, a floating energy transfer capacitor (a resonant capacitor as part of the switching cycle), and a resonant inductor.

Because traditional converters based on PWM square-wave switching use inductors and capacitors, they require complementary pairs of switches. When one switch is on, its complementary switch is off, and vice versa. Therefore, only an even number of switches is allowed, while the new hybrid switch PFC converter can use an odd number (3) of switches.

In this setup, such complementary switches do not exist. An active switch S alone controls two diodes, and their roles automatically change according to the polarity of the AC input voltage. For example, when the AC input voltage is positive, CR1 conducts during the on-interval of switch S. When the AC input voltage is negative, CR1 conducts during the off-interval of switch S. In addition, CR2 also automatically reacts according to the state of switch S and the polarity of the input AC voltage. When the AC input voltage is positive, CR2 conducts during the off-interval of switch S; when the AC input voltage is negative, CR2 conducts during the on-interval of switch S.

Therefore, the three switches can operate throughout the positive and negative half-cycles of the input AC line voltage. Therefore, this true bridgeless PFC converter can operate without a full-bridge rectifier because the converter topology actually performs the AC line rectification. Finally, the same DC output voltage is achieved in the positive and negative half-cycles of the input AC line voltage. Eliminating the full-bridge rectifier directly eliminates losses (especially for low line voltages of 85V).

The active switch S in the primary is modulated and operates at a switching frequency that is three orders of magnitude higher than the line frequency (e.g., 50kHz switching frequency for an AC line frequency of 50/60Hz). The duty cycle (D) can be defined by controlling the switch on-time and all steady-state specifications (e.g., DC conversion ratio) the DC current in the inductor L is expressed in terms of D.

The full-wave input line voltage and input line current are then sensed and sent as inputs to the bridgeless PFC IC controller. The controller modulates the primary switch S to force the input line current to be proportional to the input line voltage, thereby providing the ideal unity power factor.

The truly remarkable feature of this PFC converter is that the galvanic isolation extension allows the simplicity of the three-switch converter in Figure 10 to be maintained. The resonant capacitor is essentially split into two series capacitors with an isolation transformer inserted at their separation point. Digitally

Controlled PFC

The advent of low-cost, high-performance digital controllers for power supplies has made this type of controller available for PFC designs. Digital controllers offer programmable configuration, nonlinear control, low device count, and the ability to implement complex functions that are typically difficult to implement using analog methods.

Most of today’s digital power controllers, such as TI’s UCD3020, feature integrated power control peripherals and power management cores, including digital loop compensators, fast analog-to-digital converters (ADCs), high-resolution digital pulse-width modulators (DPWMs) with built-in dead time, and low-power microcontrollers. These controllers support complex, high-performance power supply designs such as bridgeless PFC.

For example, a bridgeless PFC can incorporate two DC-DC boost circuits: L1, D1, S1 and L2, D2, S2 (Figure 11). D3 and D4 are slow recovery diodes. Separate sensing of the line and neutral voltages referenced to the internal power ground enables measurement of the input AC voltage. By comparing the sensed line and neutral signals, the firmware can determine whether it is a positive or negative half-cycle. During the positive half-cycle, the first DC-DC boost circuit (L1-S1-D1) is active, and the boost current returns to the AC neutral line through D4. During the negative half cycle, L2-S2-D2 is the active circuit and the boost circuit returns to the AC power line through D3.


Figure 11: The digitally controlled bridgeless PFC consists of a two-phase boost circuit, but only one phase is active at a time.
Compared with a traditional single-phase PFC using the same power devices, the bridgeless PFC and single-phase PFC should have the same switching losses. However, the bridgeless PFC current only passes through one slow diode (D4 during the positive half cycle and D3 during the negative half cycle) instead of passing through two diodes at the same time. Therefore, the efficiency improvement depends on the difference in conduction losses between one diode and two diodes.

The efficiency of the bridgeless PFC can also be improved by fully turning on the inactive switch. For example, during the positive cycle, S2 can be fully turned on, while S1 is controlled by the PWM signal. Because the voltage drop across MOSFET S2 can be lower than D4 when the flowing current is below a certain value, the return current will partially or completely flow through L1-D1-RL-S2-L2 and then return to the AC power supply. This reduces conduction losses, thereby improving circuit efficiency (especially at light loads). Similarly, during the negative cycle, S1 is fully turned on, while S2 is switched on and off.

At the same AC voltage and DC output voltage, the output current is proportional to the voltage loop output. Based on this, the frequency and output voltage can be adjusted accordingly. The firmware implements the voltage loop in the digital controller. Since the output is known, it is easy to implement this function at a lower cost than the analog method.

More digital PFC controllers

Analog Devices recently released the ADP1047 and ADP1048 digital PFC controllers, which can also provide input energy measurement and inrush current control. The ADP1047 is used for single-phase PFC applications, while the ADP1048 is targeted at interleaved and bridgeless PFC applications. The

digital PFC function is based on the traditional boost circuit to provide the best harmonic correction and power factor for AC-DC systems. All signals are converted to digital signals to maximize flexibility; key parameters can be reported and adjusted through the PMBus interface.

In summary, the configuration of the ADP1047 and ADP1048 can help designers optimize system performance and maximize efficiency over the load range. Both ICs can accurately measure RMS input voltage, current, and power. This data can then be reported to the power supply’s microcontroller via the PMBus interface.

The bridgeless boost configuration of the ADP1048 eliminates the conduction losses caused by the bridge input to the PFC converter (Figure 12). In this configuration, the two power MOSFETs must be driven separately to achieve the highest efficiency. This is accomplished with a signal from the ADP1048. The IBAL pin detects the ac line phase and zero crossing. The IBAL pin is rated for a maximum voltage of VDD + 0.3 V, so the pin needs to be protected with a suitable clamp circuit.


Figure 12

During the positive ac line phase, only one boost stage is actively operating. The second stage is a passive stage; the current in Q2 flows from source to drain. Turning the Q2 FET fully on during this phase minimizes the conduction losses of Q2. When the AC line phase goes negative, the roles of Q1 and Q2 are reversed, Q2 is actively switching, and Q1 is always on. The phase information is sensed from the AC line via the IBAL pin. During the soft-start phase, both FETs are switched as a precaution. This occurs when the phase information on the IBAL pin is corrupted or inaccurate.