Analysis of chip parallel connection

1. Introduction

In order to estimate the imbalance caused by the changing parameters of parallel IGBT modules, a worst-case analysis is usually performed based on a combination of upper and lower limits of the component parameters. The disadvantage of this approach is that it does not take into account the probability of occurrence of this worst-case combination. Studying the influence of the forward voltage drop of the freewheeling diode on the current distribution of parallel modules allows the worst-case evaluation to be performed. By applying statistical methods, a more realistic derating factor can be defined.

The parallel operation of components in order to expand the current capability of a single component to meet the needs of a given application is a fundamental concept in the field of power electronics. This concept is implemented by IGBT or MOSFET chips, in which single MOS gate cells are connected in parallel to form a modern high-power chip. This connection method is also often seen in power modules, where chips are connected in parallel to achieve the required current capability.

The parallel use of conventional IGBT power modules (SKM100 GB123D) produced by SEMIKRON, a manufacturer of power electronic systems based in Nuremberg, was chosen as the subject of this investigation. In such a parallel-configured half-bridge module, both the IGBTs and the corresponding freewheeling diodes are operated in parallel. Since IGBTs have a positive temperature coefficient at rated current, they are generally considered to be very suitable for parallel connection. In contrast, the diode is more important, since the temperature coefficient of its forward voltage drop is usually slightly negative at rated current. Therefore, the following analysis only considers the current imbalance caused by the change in the freewheeling diode forward voltage drop. The analysis of the used IGBTs can also be obtained from reference ^[1] .

2. Parallel diodes for worst-case analysis

First, a worst-case analysis of parallel diodes is performed. Therefore, we assume that components with known parameters are connected in parallel and that the values ​​of the parameters are within the specification range - in our case, those modules with the maximum or minimum forward voltage drop. In order to analyze the resulting impact, the specified on-state values ​​of the modules must be converted into an analysis table. In the table, the forward voltage drop is described as a function of temperature and current, and there is also a scaling factor used to make the forward voltage drop reach the minimum, typical or maximum value. A simplified linear characteristic is chosen as the current/voltage characteristic (see Figure 1). In the parallel state, the worst-case situation occurs when the forward voltage drop of one module reaches the minimum value specified in the specification (LSL), while the forward voltage drop of one or more other modules connected to it reaches the maximum value specified in the specification (USL).

Figure 1 Simplified characteristics of the forward voltage of the freewheeling diode in a Semikron IGBT module (SKM100GB123D)
(the “dots” in the figure represent data sheet values)

[page] Assuming that there is no thermal coupling between the modules and that the junction-to-case thermal resistance of the diodes is equal to the maximum value specified in the specifications of 0.50K/W at a heat sink temperature of 85°C, the effect of the difference in forward voltage drop on the chip temperature and current imbalance caused by this difference can be calculated. To do this, start-up parameters are set for the current flowing through each chip and the temperature of the low-drop and high-drop branches (hereinafter modules with the same characteristics are referred to as "branches"). The forward voltage drop is then calculated as a function of temperature and current. This value can be used to calculate the losses; based on this, the correct chip temperature can be calculated from the thermal model. The next step is to minimize the difference between the assumed and calculated temperatures by adjusting the current flowing through each branch. Note: As a constraint, the difference in voltage drops between the branches must be zero.

For the LSL and USL branches, calculate the current and junction temperature of each chip. Rated current of the diode: 50A. For the case with only one module (n=1), choose the module at the upper specification limit because this is the worst case for a single module (Figure 2).

Figure 2 Worst case diode situation when up to 20 IGBT modules are connected in parallel: current and temperature imbalance

The chip current of a single module is 50A because there is no current imbalance. For 2 units in parallel, the current of the LSL branch is 75A, which is 50% higher than that of a single module. When the number of modules in parallel increases, the situation worsens further. When 20 modules are connected in parallel, the current reaches almost 2.25 times the rated current in the worst case.

In a single module at the upper specification limit, the junction temperature of the diode reaches 132°C. In the worst case described, the resulting unbalanced current distribution produces a dangerous junction temperature distribution in both branches. With two modules in parallel, the junction temperature is 145°C, while when 20 modules are connected in parallel, the junction temperature of the LSL branch rises to 190°C. This effect is even more severe for the diode due to its negative temperature coefficient, which is equivalent to an IGBT. The positive temperature coefficient of the forward voltage drop of the IGBT reduces the imbalance during parallel operation, while the negative temperature coefficient of the diode enhances this imbalance. Therefore, the parallel operation of multiple freewheeling diodes is considered to be critical.

3. Statistical distribution can be determined by production batch data

However, in practice, there are applications where 20 or more modules are connected in parallel, but the expected problems do not occur. This can be explained statistically. Unlike the simplified worst-case scenario described above, it is necessary to look at the probability of occurrence of the considered combination. Therefore, we need statistics on the real forward voltage drop distribution of the components used. In order to evaluate a series of production processes, it is not enough to look at the statistics of only one production batch. In fact, in general, it is necessary to consider the statistics of different production batches. Figure 3 shows the normal statistical distribution of the forward voltage drop of a batch of 125,000 diodes at I _F = 50A, with the upper and lower specification limits marked in the figure. On the basis of this statistics, we can calculate the probability of the worst-case scenario. Figure 4 shows the probability of the worst-case scenario based on the distribution function of Figure 3. The probability of finding a diode with a forward voltage drop at the upper specification limit is very low: only one diode in 10 ¹¹ has a forward voltage drop equal to or greater than the USL. The probability that one out of 10 chips is at the LSL and 9 chips are at the USL is less than 10 ^-99 . Given these numbers, it can be said that the worst-case scenario consisting of 10 chips based on a true V _{F distribution and given specification limits can almost be ruled out.}

Figure 3 Statistical distribution of forward voltage drop of 125,000 freewheeling diodes at I _{F = 50A}

Figure 4 The probability of the worst case when diodes are connected in parallel based on the normal distribution of the chip in Figure 3

Unlike the worst-case analysis, the imbalance in the current distribution can be calculated statistically for situations with a fixed probability of occurrence (such as 1ppm). Therefore, based on a given forward voltage distribution, the calculation limits are determined so that the probability of choosing a value below or above the limit is equal to the predefined probability (lower calculation limit, LCL; upper calculation limit, UCL). A more thorough analysis shows that for any normal distribution, the difference in forward voltage will reach a maximum value if and only if these limits are symmetrically defined to the mean xm of the normal distribution: xm-LCL=UCL-xm.

For setting specification limits, since the probability of occurrence drops significantly when the number of parallel chips increases, the LCL and UCL limits have to move closer to the mean of the normal distribution to maintain a constant probability of 1ppm. This makes the calculation of the current distribution imbalance caused by the chip combination fall outside the calculated limits LCL and UCL. The probability of occurrence of a poor performance combination is 1ppm. Conclusion: Only one combination out of 1 million performs worse than the results shown.

[page]4. Parallel derating factor

If the worst-case calculations performed at the outset are repeated statistically, the current and temperature imbalance results are very different (see Figure 5). For the LCL chips, the current per chip reaches a maximum of 64A at n=3 and then decreases until a complete balance is reached for the 20 parallel chips. The junction temperature reaches a maximum of about 138°C (compared to about 130°C for a single diode with high on-state losses and a probability of 1ppm).

Figure 5 Comparison of the derating factors of the worst case and statistical methods based only on the effect of the diode on-state voltage drop change with a probability of 1ppm

For a single diode (132.2°C in the worst case and 130.5°C with a probability of 1 ppm), there are only small differences in the results of the different methods (corresponding to the worst case of the statistical method), while when the number of parallel diodes increases, the calculated maximum junction temperatures differ greatly.

Based on this data, a parallel operation derating factor can be defined (specifically) to account for the change in forward voltage drop of the module in question (SKM100 GB123D). To achieve this, we first need to determine a maximum permissible temperature for parallel operation. The calculation needs to be recalculated based on the additional boundary condition that the total current flowing through the parallel group of modules is limited by the maximum permissible temperature. Once this has been done, derating curves can be defined for the worst case and statistical methods.

For the worst-case analysis, the maximum allowable junction temperature is defined as 132.2°C. This temperature is equal to the junction temperature of a single diode with a forward voltage equal to the upper specification limit. When two chips are connected in parallel, the maximum current per chip drops to 80%. When 20 chips are connected in parallel, the maximum current per chip drops to less than 40% of the rated current. Based on this calculation, 20 diodes rated at 50A can only carry 400A of current, or 20A per chip. This makes paralleling an unattractive option.

In the statistical method, the maximum permissible temperature of a single diode is 130.5°C (with a probability of occurrence of 1ppm). Therefore, this value is used as the temperature limit. When 3 diodes are connected in parallel, the maximum permissible current drops to 88%, which is the minimum value in the derating curve. For the parallel connection of more than three modules, the derating factor increases. For the parallel connection of more than 10 modules, the derating factor even exceeds 100%. At first glance, this surprising result shows that for the case of a large number of components connected in parallel, the statistical method proves that the parallel connection of components is even a more favorable method. In other words: for the same probability of occurrence, a single module is not as good as 20 modules in parallel.

It should be emphasized that this investigation focuses on the influence of only one parameter: the variation of the forward voltage drop of the freewheeling diode. The investigation demonstrates the influence of statistical methods and can be extended to more parameters. Therefore, the given derating factors only apply to the examples given. In real applications, the effects of current path asymmetry can be even more important and may require higher derating [2].

References
[1] U.Scheuermann: Paralleling of Chips–From the Classical 'Worst Case' Consideration to a Statistical Approach, Proc.PCIM, S4a3, 455-460, Nuremberg, 2005.
[2] A.Wintrich, J.Nascimento ,M.Leipenat:Influence of Parameter Distributions and Mechanical Construction on Switching Behavior of Parallel IGBT,Proc.PCIM,S4a1,511-516,Nuremberg,2006 .■