Design of a Single-stage Long Delay Circuit

Surveys show that worldwide, memory chip transactions account for about one-third of semiconductor transactions, and memory has become an important component of digital products. The storage speed and power consumption of memory have become important indicators in the research and development of memory chips. Memory circuits are divided into various types according to different applications and different storage methods, including SRAM, DRAM, ROM, EPROM, FLASH and FRAM. With the development of electronic devices, the storage capacity of electronic devices is getting larger and larger, and the storage density is getting higher and higher. The continuous development of storage density has rapidly promoted the development of semiconductor technology, making the feature size of semiconductor technology smaller and smaller. At the same time, the basic unit structure of memory has been continuously innovated and reduced, from the typical 8T, 6T to a single tube.

With the reduction of feature size, the increase of chip storage density, and the continuous improvement of memory read and write speed, the parasitic capacitance on the bit line when the memory is written has become more and more the key to the chip read speed. The large bit line capacitance causes the charging and discharging of the capacitor to become slow when reading data, which seriously restricts the memory read and write speed. Now large-scale memory data reading and writing generally requires the participation of upper and lower pre-charging and sensitive amplifiers. The types of sensitive amplifiers are divided into: voltage sensitive amplifiers and current sensitive amplifiers. The application of upper and lower precharges and sense amplifiers generally makes the reading and writing of memory use asynchronous timing for reading and writing. First, the address detector generates an address detection signal, and then the address detection signal is used to generate a series of staggered timing control signals. The control signal performs asynchronous timing control on the precharge circuit, basic storage unit, sense amplifier, and input and output latch respectively. The control signal needs to be delayed, widened, and misaligned. Due to the sharp increase in the capacity of the memory, the basic storage unit on each bit line also increases accordingly, and the capacitance on the storage bit line becomes significant. This leads to an increase in the read and write time of the sense amplifier. Therefore, the work of precharge and sense amplifier requires a wider level pulse, and the pulse of the sense amplifier must be after the precharge pulse. RC delay is used to generate a widened pulse width, and each level is widened to twice the input signal pulse width. Multiple levels of widening are required to obtain a suitable wide pulse width. In addition, using RC to generate a long delay signal requires several levels of RC circuits and a buffer is required between each level of RC. At the same time, the input pulse cannot be too narrow, otherwise the state is likely to drift away at different process corners. At the same time, multi-stage RC consumes a relatively large chip area. Based on the analysis of the principle of the traditional multi-stage RC input low pulse stretching circuit, this paper designs a single-stage long delay circuit using the single-stage idea.

1 Traditional multi-stage RC input low pulse stretching circuit

1.1 Analysis of the principle of the traditional low pulse stretching circuit

The traditional low pulse stretching circuit is shown in Figure 1. The input Vin is a low narrow pulse, and its pulse width is Win. The output of the first stage is V1, and its pulse width is W1. The output of the second stage is V2, and its pulse width is W2. The output of the i-1th stage is Vi-1, and its pulse width is VOUT. Finally, the pulse is output, and its pulse width is WOUT.

Then the pulse width after the first stage is: W1=Win+R1C1 and R1C1 The pulse width after the second stage is: W2=W1+R2C2 and R2C2 The pulse width after the i-th stage is: Wi-1=Wi-2+Ri-1Ci-1 and Ri-1Ci-1 The final output pulse width is: WOUT=Wi-1+RiCi and RiCi From the above analysis, we can know that the multi-stage RC input low pulse widening circuit first has requirements for the input pulse width. If the input pulse width is too narrow, for example, a delay of 1ns, then at least 4 levels are required to obtain a pulse width of 12ns, and the RC delay of each level must be smaller than the input low pulse width of this level, otherwise the generated output pulse width will be disconnected in the middle and divided into two separated input low pulses. At the same time, if the Vin low pulse is too narrow, the voltage of the capacitor cannot be charged to the lowest high level that causes the inverter state to flip, then one end of the AND gate input is always high, and the other end is Vin, so the input narrow pulse cannot be widened.
This RC multi-stage pulse width widening circuit requires a relatively large chip layout area. Assuming the input is a 1ns low pulse, a 5-stage RC delay widening circuit, the simulation results are shown in Figure 2.

It can be seen that narrow low pulses require multiple stages to expand to a certain pulse width, and each stage must ensure that the RC delay is less than the width of the input pulse itself, otherwise the output pulse cannot be continuous.

2 Schematic diagram of single-stage wide pulse width generation circuit

The single-stage wide pulse width generation circuit is shown in Figure 3. The basic working principle is as follows: when the input VIN is low, the P1 tube is turned on, node 2 is pulled to a high level, node 3 becomes a low level, the N3 tube is turned off, and at the same time, node 6 becomes a high level to turn on the N2 tube, pulling node 4 low. At this time, the output voltage VOUT becomes a low level. When VIN becomes high, the level of node 6 becomes low, the N2 tube is turned off, the states of nodes 2 and 3 remain unchanged, and the N3 tube is still turned off. At this time, the constant current source IDC charges the capacitor C1. When the capacitor C1 is charged to VTH, the inverter state begins to flip. When the inverter state is completely flipped, the node 5 becomes a high level, N1 is turned on, node 2 is pulled low, and VOUT becomes a high level. In this way, the low pulse is locked to VOUT, and the output VOUT will only flip when the capacitor C1 is charged to a certain value.

When C1 is charged to VC, VOUT changes from low to high, the charging time is TR, the input VIN low pulse width is WIN, and the output low pulse width is WOUT. Then:

By increasing C1, reducing IDC, and increasing TR, WOUT can be increased to achieve a low pulse width of the first level, and there is no requirement for the input pulse width. A very narrow input pulse can also be directly stretched to a very wide width. Figure 4 is the simulation waveform of the single-stage wide pulse width generating circuit.

From the simulation results, it can be seen that a 1ns low pulse is directly widened to 11ns through this circuit, and the width of the widening can be achieved by adjusting IDC and C1 according to specific requirements. And by designing a high-precision IDC, the extension can be made very accurate.

3 Conclusion

The single-stage long delay generation circuit designed in this paper has been verified in TSMC 0.35 micron process and uses a very small layout area. This long delay generation circuit has no requirements for the input low pulse width, and it can be widened in place at one time. At the same time, the accuracy can be improved by designing a precise current source and using capacitors with relatively small process deviations. This circuit is very practical in asynchronous timing control signal generation circuits, and the changes with temperature and process angle are relatively small.