DS90CF364LVDS transmitter/receiver in RGB LCD screen application

1 Introduction

Nowadays, TFF LCD screens equipped with digital RGB interfaces are widely used in notebook computers, GPS, set-top boxes, WebPads and other devices due to their clear images, simple interfaces and high brightness. However, due to the high frequency of the video signal driving the display, it cannot be directly transmitted over long distances. To this end, LVDS (Low Voltage Differential Signaling) technology can be used in the FPD (Flat Panel Display) link between the graphics controller and the LCD to overcome this problem. Actual use has proved that the transmission distance after it is connected can be expanded to about 10 meters, which fully meets the general application occasions of LCD screens.

In addition to image signals, digital RGB video signals also include signals such as line synchronization, field synchronization, and pixel clock, among which the highest frequency of the pixel clock signal can exceed 28MHz. The use of low-voltage differential signaling technology (LVDS) can fully avoid the attenuation caused by long-distance transmission and mutual crosstalk between signals. LVDS is a low-swing differential signaling technology that enables signals to be transmitted at a rate of several hundred Mbps on differential PCB line pairs or balanced cables. Its low voltage amplitude and low current drive output can ensure low noise and low power consumption. Its advantages include supporting high-speed data transmission, power saving, low noise, weak electromagnetic interference, low cost, and high integration.

2 LVDS application environment

Figure 1 shows a schematic diagram of the application environment of LVDS technology, in which the processor uses the EP7312 embedded processor with ARM core produced by CIRRUSLOGIC, the graphics control interface chip uses the SEDl356 color graphics controller of EPSON, which uses 2M bytes of EDO-DRAM, the FPD link uses the 21-bit LVDS transmitter/receiver DS90C363/DS90CF364 transmission set of National Semiconductor, the LCD screen uses the LQ64D341 18-bit TFT 6.4-inch high-brightness screen of SHARP, and is also equipped with a compatible inverter and touch screen.

SEDl356 is a display control chip for color LCD and CRT/TV that can be used with multiple CPUs and multiple DRAMs. It has 114 registers and can flexibly set various display modes. It is very powerful. The CPU bus types include SH-4/SH-3 Bus interface, MC68K Bus, MC68K Bus, MIPS/ISA, PowerPc, PC Card (PCMCIA), Philips PR31500/PR31700/ToshibaTX3912 and general type buses. It can output digital signals and analog signals (digital RGB, analog RGB and composite video) at the same time, and these two types of signals can be independent of each other, so as to manage LCD and CRT/TV at the same time and display different images. SEDl356 can support 16-color, 256-color and true color color structures. For TV circuits, the control chip can support TV NTSC and PAL display; in NTSC format, it can support multiple resolutions from 400X 396 to 720X484.

3 DS90C363/DS90CF364 Introduction

3.1 Structural characteristics

Figure 2 shows the internal structure of the DS90C363/DS90CF364 transmission chip. This chip is an 18-bit FPD link with an operating voltage of 3.3V. The overall power consumption of the chip is less than 250mW. It uses a 48-pin TSSOP package and is compact. The DS90C363 transmitter can convert 18-bit RGB data and 3-bit LCD timing and control data (FPLINE/GHS (line synchronization), FPFRAME/GVS (field synchronization), DRDY/ENAB/GHREF (horizontal display enable)) into three mixed LVDS data streams within one clock cycle, and send the pixel shift clock signal (FPSHIFT/CK) on the fourth LVDS link. Each cycle of the clock signal will sample and send the above 21-bit data and control signals. For example, at a 65MHz transmission clock frequency, the transmission rate of each LVDS channel can be as high as 455Mbps, and the data throughput is 170 megabytes per second. For ease of use, the transmitter can be set to rising or falling edge trigger through a dedicated pin. The DS90CF364 receiver can demix the received LVDS data stream and convert it into TIL/CMOS data. The falling edge trigger required by the receiver does not affect the selection of the transmitter trigger edge. The chip supports VGA, SVGA, XGA or higher resolutions. When using it, the designer does not need to change the connection relationship of the original circuit, and its maximum transmission distance can reach 10 meters.

The main features of this set are as follows:

Supports pixel shift clock in the range of 20-65MHz;
has energy-saving mode (less than 0.5mW);
bandwidth up to 170Mbyte/s;
throughput up to 1.3Gbps;
operating temperature range of -40～85℃;
has very low electromagnetic interference (EMI);
compatible with TIA/EIA-644LVDS standard;
electrostatic discharge (ESD) rate greater than 7kV.
3.2 Pin Function

Figure 3 shows the pinout of the DS90C363 and DS90CF364, where the pin functions of the transmitter DS90C363 are as follows:

TxIN0~TxIN20: TEL electrical data input, including 6 red, 6 green, 6 blue and 3 control lines - FPLINE (HSYNC), FPFRAME (VSYNC) and DRDY (Data Enable);

TxOUT+: positive terminal of LVDS differential data output;

TxOUT-: negative terminal of LVDS differential data output;

TxCLK IN: TIL level clock input, generally activates data on its falling edge.

R_FB: programmable trigger strobe;

TxCLK OUT+: LVDS differential clock output positive terminal;

TxCLK OUT-: LVDS differential clock output negative terminal;

PWR DWN: TTL level input, tri-state when set to low to ensure low current in power saving state;

Vcc: power supply pin for TTL;

GND: Power ground for TTL;

PLL Vcc: power supply pin for PLL;

PLL GND: power ground for PLL;

LVDS Vcc: power supply pin for LVDS output;

LVDS GND: Power ground for LVDS output.

The pin functions of the receiver DS90CF364 are as follows:

RxOUT0~RxOUT20: TTL level data output, including 6 red, 6 green, 6 blue and 3 control lines - FPLINE (HSYNC), FPFRAME (VSYNC) and DRDY (Data Enable). ;

RxIN+: positive terminal of LVDS differential data input;

RxIN-: negative terminal of LVDS differential data input;

RxCLK OUT: TTL level clock output, usually activating data on its falling edge;

RxCLK IN+: LVDS differential clock input positive terminal;

RxCLK IN-: LVDS differential clock input negative terminal;

PWR DWN: TTL level input, when set to low, the output is tri-state to ensure low current in power saving state;

Vcc: power supply pin for TTL;

GND: Power ground for TTL;

PLL Vcc: power supply pin for PLL;

PLL GND: power ground for PLL;

LVDS Vcc: power supply pin for LVDS output;

LVDS GND: Power ground for LVDS output.

4 Design Application

The system board design introduced in this article is not too difficult, but you need to pay attention to the following two points:

(1) PCB board design

It is best to use a 4-layer board. The order from the top layer to the bottom layer is LVDS signal layer, ground layer, power layer, and TFL signal layer. This can isolate the TIL signal and LVDS signal from each other. Otherwise, T1L may be coupled to the LVDS line. In view of the above reasons, it is best to place the TIL and LVDS signals on different layers isolated by the power/ground layer during design. When installing, the LVDS transmitter and receiver should be as close to the LVDS end of the connector as possible. When using distributed multiple capacitors to bypass LVDS devices, the surface mount capacitors should be placed as close to the power/ground layer pins as possible to better filter and prevent power supply interference. The power layer and ground layer should be laid with some thick wires as much as possible to keep the return path of the PCB ground layer wide and short. The cable of the ground layer return copper wire should be used to connect the ground layers of the two systems. Multiple vias (at least two) can be used to connect them to the power layer (line) and ground layer (line). The surface mount capacitors can be directly soldered to the via pads to reduce wire ends. All unused LVDS receiver input pins should be left floating, all unused LVDS and TIL output pins should also be left floating, and unused TIL transmit/driver input and control/enable pins should be connected to power or ground.

(2) Cable selection

When using controlled impedance media, the differential impedance is about 100Ω, so it does not introduce a large impedance discontinuity, but balanced cables (such as twisted pairs) are usually better than unbalanced cables in terms of reducing noise and improving signal quality. Most cables can work effectively when the cable length is less than 0.5m. When the distance is between 0.5-10m, CAT 3 (Categiory 3) twisted pair cables work better. Therefore, when the distance is greater than 10m and high speed is required, CAT 5 twisted pair is recommended. If you need to improve reliability in a noisy environment, it is best to use shielded cables. Each pair of cables must be close together, and a 100Ω surface mount termination resistor should be connected between the positive and negative ends of each pair of parallel wires as close to the receiver as possible. This resistor can serve to terminate the circulating current signal during design. In addition, a transformer connected in series at the receiving end can reduce interference and avoid the impact of the ground potential difference between the LVDS driver and the receiver.

The application connection diagram of the chipset is shown in Figure 4, which can be used as a reference during design.

5 Conclusion

The LVDS transmission chip introduced in this article can also be used in other control chips with digital RGB video interfaces. For other FPD link-specific LVDS transmission chips produced by National Semiconductor, the methods introduced in this article can also be used for design and debugging.