Methods for implementing digital power conversion

So what should analog engineers choose to design power supplies? The engineering answer to this question is to use intelligent digital control of the power conversion feedback loop to achieve the above functions. Microcontrollers have enabled analog designers to implement monitoring, control, communication and even deterministic functions such as power sequencing, soft start and topology control in power supplies. However, digitally controlling the entire power conversion loop is not practical due to the lack of cost-effective and high-performance technology.

1 DSC design in switching power supply

Now, a new type of digital signal controller (DSC) has made digital conversion with intelligent power peripherals possible because it uses counter-based pulse width modulation (PWM) modules, analog comparator-based feedback, and coordinated analog-to-digital converter (ADC) sampling to perform fast multiplication within a single clock cycle. This combination of features helps DSCs handle the high execution speeds required by control loop software.

Before you begin power supply design, you need to make the following decisions.

aChoose a topology that suits the application needs: step-up or step-down (Boost or Buck), isolation (forward, half-bridge or full-bridge).

b. Choose a switching technology: hard switching or soft switching. Soft switching technology (such as resonant mode or quasi-resonant mode) increases the complexity of the circuit and control in exchange for less switching loss.

c. Select a control method: voltage mode or current mode.

Voltage mode control and current mode control are two control methods based on traditional analog switching power supply (SMPS) control technology. Under voltage mode conditions, the difference (error) between the desired output voltage and the actual output voltage is used to control the time that the power supply voltage is applied to the inductor, thereby indirectly controlling the current in the inductor. Under current mode control conditions, the difference (error) between the desired output voltage and the actual output voltage is used to create a threshold value for the analog comparator to set the peak inductor current, thereby controlling the average inductor current. Voltage mode can provide higher stability in noisy environments or over a wide operating range; current mode control can achieve cycle-by-cycle current limiting and faster transient response. It also prevents "step-up inductor current" that may cause inductor saturation and cause catastrophic MOSFET failure.

d. Select the PWM operating frequency. High-frequency PWM helps use smaller inductors and capacitors, but at the expense of additional switching losses.

eDetermine the required control bandwidth. This depends largely on the load transient response expected in the application.

f allocates processor resources based on the estimated control bandwidth requirements. Although there are many control algorithms, a common technique is the proportional, integral, and derivative (PID) method. Using a common PID algorithm, the control loop will need to run at eight times the required control system bandwidth to ensure sufficient phase margin. When estimating the delay of the control loop, all delays within the control loop must be taken into account (see the "Calculating the Delay of the Control Loop" section).

Next, select a DSC that meets all or most of your design needs.

Microchip's SMPS dsPIC DSC--dsPIC30F2020 was chosen to design a synchronous buck converter. This DSC has a hard switch that provides a voltage control mode with a complementary PWM mode. This buck converter (see Figure 1) uses synchronous switching and replaces the rectifier in the circuit with a MOSFET because it has a much lower forward voltage drop than a standard rectifier. By reducing the voltage drop, the overall efficiency of this buck converter can be improved by 5%~10%. Synchronous switching with Q2 requires a secondary PWM signal to complement the primary PWM signal. When Q1 is turned off, Q2 is turned on, and vice versa. In addition, during the rising and falling edges of the PWM signal, "dead zone" control is required to prevent Q1 and Q2 from being turned on at the same time.

The relationship between the input and output voltage of a buck converter can be expressed as:

VOUT = VIN (D, where D = PWM duty cycle = TON/(TON + TOFF)

The ideal output voltage of a buck converter is the product of the input voltage and the transistor duty cycle. By detection (see Figure 1), if transistor Q1 is normally on, the output voltage will be equal to the input voltage. If Q1 is normally off, the output voltage will be zero. In reality, when the load current increases, the voltage drop across the transistor and inductor will increase. Figure 2 shows how to design a digital SMPS control system using DSC.

The sample-and-hold (S/H) circuit typically samples every 2 to 10 ms, and the ADC requires about 500 ns to convert the analog feedback signal into a digital value. The PID controller is a program that runs on the DSC and has a computational delay of about 1 to 2 ms. The controller output can be converted into a PWM signal, which drives the switching circuit. When entering a new duty cycle, if the PWM generator does not update its output immediately, a significant delay may occur. The transistor driver and associated transistors also introduce a delay of about 50 ns to 1 microsecond, which varies depending on the device used and the circuit design.

2 Calculating the delay of the control loop

The total control loop delay is the sum of the ADC sampling and conversion time (500ns), the PID calculation time (1μs), the PWM output delay (0), the transistor switching time (50ns), and the PID execution speed period (2μs). The total loop delay in this example is 3.65μs, which means the maximum effective control loop sampling rate is 274kHz. Although the Nyquist theorem requires a 2x sampling rate to reconstruct a signal, a digital control loop must still sample at 6x to 10x the sampling rate. The reason for this is that with only a 2x sampling rate, the phase lag will be 180 degrees. With a 2x sampling rate, we have already used up the 180-degree phase lag "budget" without considering any other delays in the system. A system using an 8x sampling rate introduces 45 degrees of phase lag in the sampling process alone, which is a much better sampling rate. In order to have sufficient phase margin, many digital control systems oversample the analog signal by 10 times or more. Assuming the highest effective sampling rate is 274kHz, the effective control bandwidth is one-eighth of that, or about 34kHz.

3 Importance of PWM in SMPS Design

Different power supply specifications drive the need for different power supply topologies, which require different PWM modes, each of which supports a variety of SMPS designs, including standard, complementary, push-pull, multi-phase, variable phase, current reset, and current limit PWM modes. The most basic PWM mode is standard edge-aligned PWM, where the ratio of on-time to off-time controls the supply current. Only one PWM output from each pair of outputs is used in these asynchronous buck, boost, and flyback converter circuits. Synchronous buck converters use complementary PWM mode, where the complementary output controls a "synchronous switch" rectifier implemented by MOSFETs instead of the usual rectifier. Complementary PWM mode can also be used in other circuits that use synchronous rectification to improve system efficiency.

Push-pull converters are commonly used in DC/DC converters and AC/DC power supplies. The term "multi-phase PWM" describes the multiple PWM outputs that are not edge-aligned. Multi-phase converter circuits are often used in DC/DC converters in applications where high currents must be supplied and load changes may occur very quickly. Phase-shifted PWM modes are becoming more common due to the widespread use of PC power supplies. Microchip's dsPIC DSC SMPS family can support all known PWM modes currently used in the power supply industry.

4 Understanding PWM Resolution

Power supply designers and customers must correctly understand the term "PWM resolution". PWM resolution does not refer to how wide a counter is, but rather how many counts can occur within the PWM cycle period (the smallest possible PWM time slice). In the power supply industry, PWM resolution refers to the smallest time increment within the PWM duty cycle. This resolution is often expressed in nanoseconds. If a PWM module does not have sufficient resolution, the control system (hardware or software) will jitter the PWM output to achieve the desired average output. In power supply applications, PWM jitter can cause ripple current problems and cause the control to enter an undesirable operating mode called "limit cycling".

For example, suppose the output of the control loop requires a value of 3.25, and the values ​​the PWM can output are 3 and 4. In this case, the PWM jitters between the values ​​of 33343334. This can be easily seen - many DSCs use PWM counters running in the 40 to 150MHz range, which can produce PWM resolutions of 6 to 25ns. The SMPS dsPIC DSC family has a duty cycle resolution of 1ns. In a control loop, the acquisition time from the voltage and current measurements before the PWM outputs a new duty cycle value is called "latency." When latency is reduced, the control loop becomes more stable and more responsive. Some DSCs are equipped with PWM modules that only accept new duty cycle data on a PWM cycle-to-cycle basis. The time lag in the software calculating the new duty cycle value before the PWM module receives the data can increase control loop latency and make it less stable. Therefore, it is best to use a DSC with a PWM module that can receive and process new duty cycle data in a timely manner.

5 Requirements for SMPS ADC

You can apply your analog knowledge to intelligent power supply design using DSCs. On-chip ADCs can provide system status (feedback) to the control loop. Traditional ADCs are designed based on the assumption that ADC values ​​are sampled and processed in "groups". ADCs in audio processing and industrial control systems often function in this manner. Group sampling can cause the processor workload to peak in the group, which will increase the latency of the control loop.

In SMPS circuits, there is usually no analog signal to be sampled and converted, or such a signal is not so obvious at all times. Such a signal may be more obvious at a certain moment in the PWM cycle. Therefore, due to inaccurate sampling timing, the standard ADC module may miss the desired data.

Figure 3 shows an example circuit of a current sense resistor for monitoring current. In this circuit, current can be detected only when the transistor is turned on. Typical ADC modules cannot accurately enable the sample-and-hold circuit to perform a sample at the appropriate time. If the application requires multiple circuits for detection, then this ADC is not ideal. The on-chip ADC module of the SMPS dsPIC DSC provides independent sample-and-hold circuits that can perform independent sampling. Therefore, it can monitor voltage or current at the exact moment, help implement the sampling of event transient signals, and reduce system cost. In addition, the on-chip ADC of the SMPS dsPIC device can perform asynchronous sampling, which helps support multiple control loops operating at different frequencies such as PFC (70 kHz) and DC/DC (250 kHz).

6 Analog comparators improve digital SMPS design

Because the ADC cannot continuously monitor the signal, it can only sample at up to a megasample per second (MSPS). Some DSCs have analog comparators that free up the processor and ADC to perform other important tasks. For example, the analog comparator can be used to control current in a similar way to how a traditional linear power supply controller directly controls the PWM duty cycle. The analog comparator can also provide independent monitoring of overvoltage or overcurrent conditions. The reference DAC and analog comparator of Microchip's SMPS dsPIC DSC can achieve a delay of about 25ns from current measurement to PWM update. Typically, it takes about 25ns from the time the analog voltage is detected until the PWM output is modified by the comparator. This response time is very fast compared to other ADCs that must use "polling" techniques and other DSCs that use the processor to modify the PWM output in response to changing conditions. In fact, this is how DSCs implement cycle-by-cycle current limiting, which is current mode control. Because the reference DAC connected to the analog comparator is also 16-bit, the PWM resolution is the same, so the same control resolution is valid for both voltage and current mode.

7 PID Algorithm

Using the PID algorithm, the error between the actual and desired output voltages is proportionally, integrally, and differentially calculated, and then these three terms are combined to control the PWM duty cycle. The PID algorithm can be used for both voltage and current mode control loops. No DSP skills are required to process Microchip's DSC (see the code listing in Figure 5), and the main "core" of the control software (Figure 4) is the PID loop. PID software is usually small, but its execution speed is very fast, usually iterating hundreds of thousands of times per second. This high repetition rate requires the PID software program to perform as efficiently as possible to achieve the best performance. Using an assembler is a good way to ensure "tight code."

The PID control loop is periodically interrupt driven by the ADC. Any system function can be executed in the "idle loop" to reduce unnecessary work in the PID control software. Functions such as voltage rise/fall, error detection, feedforward calculation and communication support routines are all executable in the idle loop. Other interrupt driven processes must have a lower priority than the PID loop.

The idle loop starts after completing system and peripheral initialization tasks. Typically, the idle loop monitors temperature, calculates "feedforward" conditions, and checks for fault conditions. The SMPS software can execute the control algorithm, with the ADC interrupt-driven PID loop as its most time-sensitive portion. The PID software should not use more than approximately 66% of the available processor bandwidth so that the remainder of the computational resources can be allocated to the idle loop software.

Assuming a PID loop (30 instructions) running at 30 MIPS, the execution time is about 1μs. If the repetition rate is 500kHz (2μs), the PID workload consumes half of the available processor bandwidth, or 15MIPS.

Example code listing for PID software for digital buck converter:

CALCULATE_PID:

push.s ; Save SR and W0-W3

bclr.b IFS0+1, #3; Clr IRQ flag in interrupt controller

#PID_REG_BASE, w8 ; Init pointer to PID register block

mov #PID_GAIN_REG_BASE, w10; Init pointer to PID gain register block

mov ADBUF1, w0 ; Read ADC to get voltage measurement

mov COMMANDED_VOLTAGE, w1 ; Get commanded output voltage

sub w1, w0, w0 ; W0 = proportional voltage error

mov PROPORTIONAL_Error, w1 ; Get previous voltage error

sub w0, w1, w2; diff error = new verr - old verr

mov w0, PROPORTIONAL_ERROR ; Store New Proportional Voltage Error

mov w0, PREINTEGRAL_TERM ; Store copy PERR as pre integral term

mov w2, DERIVATIVE_ERROR ; Store new Derivative Error

; These registers are reserved for PID calculations

; w6, w7 = contains data for MAC operations

; w8, w10 = pointers to error terms, and gain coefficients

SUM_PID_TERMS:

clr A, [w8]+=2, w6, [w10]+=2, w7; clr A, prefetch w6, w7

mac w6*w7, A, [w8]+=2, w6, [w10]+=2, w7; MAC proportional term and gain

mac w6*w7, A, [w8]+=2, w6, [w10]+=2, w7 ; MAC derivative term and gain

mac w6*w7, B, [w8]+=2, w6, [w10]+=2, w7; Update Integrator

add ACCA; Add ACCB (Integrator) to ACCA

sftac A, -#8; scale accumulator (shift)

mov ACCAH,w0 ; Read MSW of acca (result)

btst ACCAU,#7 ; Check sign bit of ACCA

bra z, Output_PWM; Branch if acca PWM value is positive

clr w0; Clear negative PWM values

OUTPUT_PWM:

mov w0, DC1 ; Output new duty cycle value

pop.s ; Restore SR, w0-w3

retfie; Return from Interrupt

Evaluation boards help designers test and modify SMPS control software and understand the design principles of SMPS. In this case, you can consider using Microchip's dsPICDEM SMPS Buck Development Board, an excellent low-power DC/DC buck converter, to evaluate DSC devices and control software. The board can obtain its input power from a standard AC/DC 9V, 0.75A power supply. There are two independent buck converters on the board, and the demonstration software is set up to provide outputs up to +5V and +3.3V.

Figure 4 Control software structure

The input voltage range of this development board is 8-14V DC. Each output load should be limited to 0.75A, and input power can be provided through the coaxial input power connector J2 or the test clip connections P1 and P2. The board can also provide a dynamic load to the +5V output. This load is driven by a 1kHz square wave signal generated by the output compare module. The on-board dynamic load uses a FET to connect a resistor load to the converter output to ground, achieving converter excitation so that the dynamic behavior of the converter can be measured. The use of the dynamic load is user-selectable through jumper blocks and/or software.

The user can choose to run the board as a standard buck converter or a synchronous buck converter via jumper settings. The software provided can run the board in voltage control mode or current monitoring. The board can also measure current through a sense resistor at the output of the converter, while the voltage is amplified and sent to the ADC input of the dsPIC30F2020 device. The board also provides three spare variable resistors that can be read through the ADC input. These "potentiometers" can be used to simulate the desired signals in prototyping.

8 Conclusion

With the new DSCs designed specifically for digital loop control, power supply designers can easily add new features and capabilities to their designs. To do this, there is no need to learn complex digital signal processor (DSP) processing techniques. Using familiar analog components and software, designers can quickly and economically use DSCs to develop power supplies with greater intelligence.