Power management design based on PLL technology

summary

Phase-locked loops (PLLs) are the basic building blocks of modern communication systems. PLLs are commonly used in radio receivers or transmitters, primarily providing the "local oscillator" (LO) function; they can also be used for clock signal distribution and noise reduction, and are increasingly used as clock sources for high sampling rate analog-to-digital or digital-to-analog conversion. As the noise performance of each generation of PLLs improves, the impact of power supply noise becomes more and more significant, and in some cases can even limit the noise performance.

This article discusses the basic PLL scheme shown in Figure 1 and examines the power management requirements of each building block.

Figure 1. Basic phase-locked loop showing various power management requirements

In a PLL, a feedback control loop drives a voltage controlled oscillator (VCO) so that the oscillator frequency (or phase) accurately tracks multiples of an applied reference frequency. Many excellent references, such as Best's Phase-Locked Loops1, explain the mathematical analysis of PLLs; simulation tools such as ADI's ADIsimPLL? are helpful in understanding loop transfer functions and calculations. Let's examine each PLL building block in turn.

VCO and VCO Pushing

A voltage controlled oscillator converts the error voltage from the phase detector into an output frequency. The "gain" of the device is defined as KVCO, usually expressed in MHz/V. Voltage controlled variable capacitance diodes (varactors) are often used to adjust the frequency within the VCO. The gain of the VCO is usually high enough to provide adequate frequency coverage, but not high enough to reduce phase noise, because any varactor noise will be amplified by KVCO times, thereby increasing the output phase noise.

The advent of multiband integrated VCOs, such as those used in the ADF4350 frequency synthesizer, eliminates the trade-off between KVCO and frequency coverage, allowing PLL designers to use an IC that contains several medium-gain VCOs and an intelligent band-switching routine that selects the appropriate band based on the programmed output frequency. This band splitting provides a wide overall range and lower noise.

In addition to the need to convert input voltage changes to output frequency changes (KVCO), power supply fluctuations also introduce interference components to the output frequency changes. The sensitivity of the VCO to power supply fluctuations is defined as the VCO pushing (Kpushing), which is usually a small fraction of the required KVCO. For example, Kpushing is usually 5% to 20% of KVCO. Therefore, for high-gain VCOs, the pushing effect is increased and the noise contribution of the VCO power supply becomes more important.

VCO pushing is measured by applying a dc tuning voltage to the VTUNE pin, varying the supply voltage, and measuring the change in frequency. The pushing factor is the ratio of the change in frequency to the change in voltage, as shown in Table 1, using the ADF4350 PLL.

Table 1. ADF4350 VCO Push-Stress Test

Another approach, mentioned in Reference 2, is to dc-couple a low-frequency square wave into the supply while observing the frequency-shift keying (FSK) modulation peaks on either side of the VCO spectrum (Figure 2). The peak-to-peak frequency deviation divided by the square wave amplitude gives the VCO pushing factor. This measurement is more accurate than static dc testing because any thermal effects associated with dc input voltage variations are eliminated. Figure 2 shows a spectrum analyzer plot of the ADF4350 VCO output at 3.3 GHz with a 10 kHz, 0.6 V pp square wave applied to the nominal 3.3 V supply. For a pushing factor of 1.62 MHz/0.6 V or 2.7 MHz/V, the resulting deviation is 3326.51 MHz – 3324.89 MHz = 1.62 MHz. This result can be compared to the static measurement of 2.3 MHz/V in Table 1.

Figure 2. ADF4350 VCO response to a 10kHz, 0.6V pp square wave.

Spectrum analyzer plot of power supply modulation

In a PLL system, higher VCO pushing means a greater increase in VCO supply noise. To minimize the impact on VCO phase noise, a low noise power supply is required.

References 3 and 4 provide examples of how different low dropout regulators (LDOs) affect PLL phase noise. For example, the performance of the ADP3334 and ADP150 LDOs when powering the ADF4350 is compared. The integrated rms noise of the ADP3334 regulator is 27 μV (over 40 years, from 10 Hz to 100 kHz). This result can be compared to the 9 μV of the ADP150 LDO used on the ADF4350 evaluation board. The difference in the measured PLL phase noise spectral density can be seen in Figure 3. The measurements were made using a 4.4 GHz VCO frequency with the VCO pushed to maximum (Table 1), and are therefore worst-case results. The ADP150 regulator noise is low enough that the contribution to the VCO noise is negligible, which is confirmed by repeating the measurement using two (assumed “noiseless”) AA batteries.

Figure 3. Phase noise comparison of the ADF4350 at 4.4 GHz when powered by the ADP3334 and ADP150 LDO pairs (AA batteries).

Figure 3 highlights the importance of a low noise power supply for the ADF4350, but what about the noise requirements for the power supply or LDO?

Similar to the VCO noise, the LDO phase noise contribution can be viewed as an additive component, LDO(t), as shown in Figure 4. Again using the VCO excess phase expression we get:

Or in the frequency domain:

where vLDO(f) is the voltage noise spectral density of the LDO.

The single-sideband power spectrum density SΦ(f) in a 1 Hz bandwidth is given by:

When expressed in dB, the formula used to calculate the phase noise contribution due to power supply noise is as follows:

(1)

where L(LDO) is the regulator noise contribution to the VCO phase noise (expressed in dBc/Hz) at an offset of f; f; Kpushing is the VCO pushing factor, expressed in Hz/V; and vLDO(f) is the noise spectral density at a given frequency offset, expressed in V/√Hz.

Figure 4. Small signal additive VCO power supply noise model

In a free-mode VCO, the total noise is the LLDO value plus the VCO noise. Expressed in dB, this is:

For example, consider a VCO with a pushing factor of 10 MHz/V and a phase noise of –116 dBc/Hz measured at 100 kHz offset: What is the required power supply noise spectral density to not degrade the VCO noise performance at 100 kHz? Power supply noise and VCO noise add as a root sum of squares, so the power supply noise should be at least 6 dB below the VCO noise to minimize the noise contribution. So the LLDO should be less than –122 dBc/Hz. Using Equation 1,

Solving for vLDO(f),

At 100 kHz offset, vLDO(f) = 11.2 nV/√

The LDO noise spectral density at a given offset can usually be read from the typical performance curves in the LDO data sheet.

When the VCO is connected inside a negative feedback PLL, the LDO noise is high-pass filtered by the PLL loop filter in a similar manner to the VCO noise. Therefore, the above equation only applies to frequency offsets greater than the PLL loop bandwidth. Within the PLL loop bandwidth, the PLL can successfully track and filter the LDO noise, thereby reducing its noise contribution.

LDO Filtering

To improve LDO noise, there are generally two options: use an LDO with less noise, or post-filter the LDO output. The filtering option may be a good choice when the noise requirements without a filter exceed the capabilities of an economical LDO. A simple LC π filter is often sufficient to reduce the out-of-band LDO noise by 20 dB (Figure 5).

Figure 5. LCπ filter for attenuating LDO noise.

Part selection requires great care. Typical inductors are in the microhenry range (using ferrite cores), so the saturation current (ISAT) specified in the inductor data sheet needs to be considered as the DC level at which the inductance drops by 10%. The current consumed by the VCO should be less than ISAT. Effective series resistance (ESR) is also an issue because it causes an IR drop across the filter. For a microwave VCO consuming 300 mA DC, an inductor with an ESR of less than 0.33 Ω is required to produce an IR drop of less than 100 mV. Low non-zero ESR also dampens the filter response and improves LDO stability. For this reason, it may be practical to select capacitors with very low parasitic ESR and add a dedicated series resistor. This approach can be easily simulated in SPICE using a downloadable device evaluator such as NI Multisim?. .

Charge Pumps and Filters

The charge pump converts the phase detector error voltage into current pulses that are integrated and smoothed by the PLL loop filter. The charge pump can typically operate at voltages up to 0.5 V below its supply voltage (VP). For example, if the maximum charge pump supply is 5.5 V, then the charge pump can only operate up to 5 V output voltage. If the VCO requires a higher tuning voltage, an active filter is usually required. For useful information and reference designs on actual PLLs, see Circuit Note CN-0174,5 and for ways to handle high voltages, see Designing a High-Performance Phase-Locked Loop with a High-Voltage VCO,"6 which appeared in Analog Dialogue, Volume 43, Number 4 (2009). An alternative to an active filter is to use a PLL and a charge pump designed for higher voltages, such as the ADF4150HV. The ADF4150HV can operate with charge pump voltages up to 30 V, eliminating the need for an active filter in many cases.

The low power consumption of the charge pump makes it seem attractive to use a boost converter to generate a high charge pump voltage from a lower supply voltage, however the switching frequency ripple associated with this type of DC-DC converter can produce unwanted spurious tones at the output of the VCO. High PLL spurs can cause transmitter emission shielding testing to fail, or degrade sensitivity and out-of-band blocking performance within a receiver system. To help guide the specification of the converter ripple, a comprehensive power supply rejection plot vs. frequency was obtained for various PLL loop bandwidths using the measurement setup of Figure 6.

Figure 6. Setup for measuring charge pump power supply rejection

A 17.4 mV (–22 dBm) ripple signal was ac-coupled to the supply voltage and swept over frequency. The spurious level was measured at each frequency and the PSR was calculated as the difference (in dB) between the –22 dBm input and the spurious output level. The 0.1 μF and 1 nF charge pump supply decoupling capacitors left in place provide some attenuation to the coupled signal, so the signal level at the generator increases until 17.4 mV is measured directly at the pin at each frequency point. The results are shown in Figure 7.

Within the PLL loop bandwidth, power supply rejection initially deteriorates as frequency increases. As the frequency approaches the PLL loop bandwidth, the ripple frequency is attenuated in a manner similar to the reference noise and the PSR improves. This graph shows that a boost converter with a higher switching frequency (ideally greater than 1 MHz) is required to minimize the switching spurs. In addition, the PLL loop bandwidth should be minimized as much as possible.

At 1.3 MHz, the ADP1613 is a suitable boost converter. If the PLL loop bandwidth is set to 10 kHz, the PSR may reach about 90 dB; with a loop bandwidth of 80 kHz, the PSR is 50 dB. After first solving the PLL spurious level requirements, you can work back to determine the required ripple level at the boost converter output. For example, if the PLL needs less than –80 dBm spurs and the PSR is 50 dB, the ripple power at the charge pump supply input needs to be less than –30 dBm, or 20 mV pp. If sufficient decoupling capacitors are placed close to the charge pump supply pins, the above level of ripple voltage can be easily achieved using ripple filters. For example, a 100 nF decoupling capacitor can provide more than 20 dB of ripple attenuation at 1.3 MHz. Care should be taken to use capacitors with appropriate voltage ratings; for example, if the boost converter generates an 18 V supply, capacitors with a 20 V or higher rating should be used.

Figure 7. ADF4150HF charge pump power supply rejection curve

The design of the boost converter and ripple filter can be simplified using the Excel-based design tool ADP161x. Figure 8 shows the user input for a 5 V input to 20 V output design. To minimize the voltage ripple at the output of the converter stage, the design selects the noise filter option and sets the VOUT ripple field to the minimum value. The high voltage charge pump consumes 2 mA (maximum), so OUT is 10 mA to provide margin. The design uses a PLL loop bandwidth of 20 kHz and was tested with the ADF4150HV evaluation board. Based on Figure 7, a PSR of about 70 dB is possible. Due to the excellent PSR, this setup does not present significant switching spurs (< –110 dBm) at the VCO output, even when the noise filter is omitted.

Figure 8. ADP1613 boost converter EXCEL design tool

As a final experiment, the PSR of the high voltage charge pump was compared to an active filter, the most common topology currently used to generate high VCO tuning voltages. To perform the measurement, an ac signal with an amplitude of 1 V pp was injected into the charge pump supply (VP) of the ADF4150HV using a passive loop filter, identical to the measurement setup of Figure 6. The same measurement was then repeated with an active filter replacing the passive filter of equal bandwidth. The active filter used was model CPA_PPFFBP1, as described in ADIsimPLL (Figure 9).

Figure 9. Screen view of the CPA_PPFFBP1 filter design in ADlsimPLL

To provide a fair comparison, the decoupling on the charge pump and op amp supply pins is identical, i.e., 10 μF, 10 nF, and 10 pF capacitors in parallel. The measured results are shown in Figure 10: the switching spurious levels of the high voltage charge pump are reduced by 40 dB to 45 dB compared to the active filter. The improved spurious levels with the high voltage charge pump can be explained in part by the lower loop filter attenuation seen by the active filter, where the injected ripple is after the first pole, whereas in the passive filter the injected ripple is at the input.

Figure 10. Power supply ripple levels for active loop filter and high voltage passive filter

One final note: The third supply rail (divider supply, AVDD/DVDD) shown in Figure 1 has more relaxed supply requirements than the VCO and charge pump supplies, because the RF portion of the PLL (AVDD) is typically a bipolar ECL logic stage with a stable bandgap reference bias voltage, and is therefore relatively immune to supply effects. Additionally, digital CMOS blocks are inherently more immune to supply noise. Therefore, it is recommended to select a moderate performance LDO (DVDD) that can meet the voltage and current requirements of this rail, and to provide adequate decoupling close to all supply pins; typically 100 nF and 10 pF in parallel are sufficient.

Conclusion

The power management requirements for the major PLL blocks have been discussed above, and the specifications have been derived for the VCO and charge pump supplies. Analog Devices provides a variety of design support tools for power management and PLL ICs, including reference circuits and solutions, as well as various simulation tools such as ADIsimPLL and ADIsimPower. By understanding the impact of power supply noise and ripple on PLL performance, designers can work back to derive the specifications of the power management blocks and achieve the best performing PLL design.