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Published on 2020-3-10 20:42
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This post is from stm32/stm8
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This post was last edited by freebsder on 2020-3-10 23:35
Timing is timing, interrupt is interrupt. It can be said that all communication physical layers or protocol request layers above have timing requirements, it's just a matter of length.
You seem to need to consider the timing duration and whether the microcontroller (or other) processing performance can keep up. Consider an extreme case, the sender sends byte data at a frequency of 50MHz to the receiver, and the receiver's processing frequency is also 50MHz. At this time, the receiver can't do anything except taking data out of the fifo. What do you want the microcontroller to do at this time? Change the scene, the sender is still 50MHz, and the receiver is now a 3G CPU. Your speed is only 1/60 of it. The CPU can do a lot of things besides your protocol.
Any physical layer communication cannot be transient, it cannot be without duration, it cannot be infinite frequency, and the frequency always has its reciprocal. Even the most hard real-time system has a response time indicator. If you are
sure that your system meets the hard real-time requirements, when the microcontroller has little surplus (more than 10 times), there is generally only one way to deal with it, which is to turn off the interrupt deadlock polling.
Resources determine your means. If you don’t have enough resources, don’t think too much.
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Published on 2020-3-10 23:32
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Published on 2020-3-10 21:41
Only look at the author
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Published on 2020-3-10 21:50
Only look at the author
This post is from stm32/stm8
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There is a chip that uses a single line to send and receive data, and has strict timing requirements. If the communication is interrupted, it is equivalent to lengthening the timing, causing the communication rate to be inconsistent with the original, and then the communication will fail. If you use __disable_irq(); __enable_irq
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Published on 2020-3-10 23:06
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