Reliability Design of Multi-Power Supply in High-Precision Measurement System Based on DSP/FPGA

Since the high-precision measurement system has a high operating frequency, a large amount of data processing, and relatively high power consumption, and the quality of the power supply system directly affects the stability and accuracy of the system, it is of great practical significance to design a high-efficiency and high-reliability power supply system. This article mainly describes the power supply design of an actual high-precision measurement system.

1 Power supply requirements for DSP and FPGA

The system uses Altera's Cyclone series EPIC12 model FPGA and TI's TMS320C6713B model DSP, both of which require two power supplies [1-2]: the peripheral I/O voltage is 3.3V and the core voltage is 1.5V and 1.2V respectively. Therefore, their coordination issues must be considered: (1) During the power-on process, it is necessary to ensure that the core is powered first and the peripheral I/O is powered later. The core should be powered on at the same time as the peripheral I/O interface power supply. Otherwise, large current may appear at the output end of the DSP and FPGA, which will greatly affect the service life of the device and even damage the device. (2) When turning off the power, the core should be powered off at the same time as the peripheral I/O interface power supply, and the I/O interface power supply should be turned off first, and then the core power supply. This paper mainly uses TI's TPS5431× series products to generate 1.2V, 1.5V and 3.3V voltages[3].

All power conversion chips in the system are powered by batteries. When the power module is powered by batteries, its voltage may fluctuate severely during the rise process and before reaching a stable state. If the voltage of DSP and FPGA fluctuates greatly during the power-on process, loading may fail and cause subsequent loading operations to be abnormal[4]. In order to ensure successful loading and not produce uncontrolled states, voltage monitoring and reset circuits are added to the system to ensure that DSP and FPGA chips are always in a reset state during the system power-on process until the voltage reaches the required level. At the same time, once the voltage of the power supply drops below the threshold, the chip is forced to enter the reset state to ensure that the system works stably. Because the system is powered by a 6V battery, the voltage will not exceed 6V, and only undervoltage monitoring is required[5].

2 Power system design

There are analog circuits and digital circuits in the system. This paper focuses on the digital circuit power supply part.

This design uses the TPS5431× series voltage conversion chip to design a digital power system, which generates the core and peripheral voltages of the DSP and PFGA as well as the +5V voltage. The TPS5431× series is a synchronous PWM Buck voltage converter with low voltage input and high current output. It has few peripheral components in the circuit, and the 60mΩ MOSFET switch tube ensures a high efficiency of more than 92% at a continuous output current of 3A; the output voltage is optional at 0.9V, 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V, with an initial error of 1%; the PWM frequency range is from 280 to 700kHz; overload protection is achieved through peak current limiting and thermal shutdown; the heat-enhanced PWP package provides better heat dissipation for the chip; and the circuit board area and cost are comprehensively solved [3].

2.1 Core voltage generation

This part mainly designs the core power supply system for TMS320C6713B and EPIC12. The core voltages are 1.2V and 1.5V respectively, which are generated by TPS54312 and TPS54313 respectively. The specific circuits are shown in Figure 1 and Figure 2. In order to meet the power supply sequence requirements, PWRGD in Figure 1 and Figure 2 is connected to the SS/ENA pin in Figure 3.

Parameter selection: The switching frequency of the chip is set to 700kHz. To this end, it is necessary to keep the FSEL pin open and connect a 71.5kΩ resistor in series between the RT pin and the AGND pin. The value range of the output filter inductor is between 4.7 and 10μH. This article uses a 4.7μH chip inductor. The SS/ENA pin is grounded through a low-capacitance capacitor, which has the functions of enabling, output delay, and voltage rise delay. The delay time is proportional to the capacitance value, which is approximately:


Where: td is the output delay time (seconds); C(SS) is the capacitance connected to the SS/ENA pin (F); t(SS) is the output voltage rise delay time (seconds).

In the core voltage circuit of this design, C(SS) = 0.039μF. According to formula (1) and formula (2), td and t(SS) are 9.36ms and 5.46ms respectively.

2.2 Generation of peripheral voltage and realization of power supply sequence

TPS54316 is used to generate a 3.3V output voltage. The selection of peripheral device parameters is the same as the core voltage circuit except for the capacitor at the SS/ENA pin. The peripheral I/O voltage circuit is shown in Figure 3.

In order to realize the power supply sequence of the core and peripheral I/O interface, this paper adopts the method of adjusting the capacitance value at the SS/ENA pin and using the PWRGD and SS/ENA signals in TPS5431× to control. On the one hand, C(SS)=0.1μF is selected in the peripheral voltage circuit. According to equations (1) and (2), td and t(SS) are 24ms and 14ms respectively. When powering on, the core is powered on about 23ms earlier than the periphery. On the other hand, even if the capacitor is broken down, at the beginning of powering on, since the output of TPS54312 and TPS54313 does not reach the threshold (95% of the normal value), PWRGD (signal) outputs a low level, and TPS54316 is in a closed state until the core voltage stabilizes. This ensures that the core is powered on first. When the power is turned off, since the outputs of TPS54312 and TPS54313 are lower than the threshold, the PWRGD signal outputs a low level, turning off TPS54316, ensuring that the peripheral I/O is powered off first. The experimental measurement shows that the peripheral I/O is powered off about 10ms earlier. It can be seen that the power supply sequence requirements are met from both aspects [6]. The experimental waveforms of the power-on process and the power-off process are shown in Figures 4 and 5 respectively.

2.3 Voltage monitoring and reset circuit

The voltage monitoring and reset circuit is implemented using TI's TPS3307-18D. TPS3307-18D is a microprocessor power monitoring chip that can output high-level and low-level reset signals at the same time, and can monitor three independent voltages at the same time: 3.3V/1.8V/adjustable voltage (the corresponding threshold values ​​are 2.93V/1.68V/1.25V). Since the reset signals of the DSP, FPGA and Flash memory in the system are all low-level valid, the signal of TPS3307-18D is used to achieve reset, and the signal is used to complete the reset indication function, and the three voltages of 3.3V, 1.5V and 1.2V (amplified to 3.6V) in the system are monitored. The voltage monitoring and reset circuit is shown in Figure 6.

As long as its own power supply voltage is above 2V and one of the three monitored voltages is lower than its threshold value, it can ensure the output of a valid RESET signal; before the values ​​of the three voltages are all higher than the threshold value, the reset signal is always valid. In addition, the chip also has a manual reset signal, which can be easily reset manually through the reset button.

The experimental test results show that the power supply system can reliably provide a stable power supply for this measurement system, and has the characteristics of fast dynamic response (25ms), high power (up to 18W), high conversion efficiency (up to 93%), small output voltage ripple (0.05V) and good voltage regulation (0.1%). However, the circuit power-on failure caused by power supply fluctuations and power-on sequence is only one aspect of power supply reliability. Therefore, the practical application examples given in this article may not be suitable for all situations. Its purpose is to remind designers of the potential risks in the power supply design for reference.