This article will take Supertex's HV9911 as an example to provide readers with relevant information on the design of boost-type high-brightness LED backlight driver circuit.
■Boost circuit design features
The boost circuit is used to drive the series voltage of the LED higher than the input voltage (Figure 1), and has the following features:
1. This circuit can be designed to operate at an efficiency higher than 90%.
2. M=SFET (Source) and the LED string share the same ground, which simplifies the detection of LED current (unlike the buck circuit, which must select the upper FET drive circuit or the upper current detection. However, the boost circuit also has some disadvantages, especially for LED driving, due to the low dynamic impedance of the LED string).
3. The input current is continuous, making the filtering of the input current much simpler (and easier to meet the requirements of the conducted EMI standard).
4. The damage of the FET used for shutdown will not cause the LED to be burned.
5. The output current of the boost circuit is a pulse waveform, so the output capacitor must be increased to reduce the ripple current of the LED string.
6. However, too large an output capacitor makes PWM dimming control more challenging. When the boost circuit is controlled to turn on and off to achieve PWM dimming control, it means that the output current will be charged and discharged in each PWM dimming control cycle, which will increase the rise and fall time of the LED string current.
7. The peak current control boost circuit is not able to control the LED current. A closed loop method is required to stabilize the circuit, which makes PWM dimming control more complicated. The control circuit must increase the bandwidth to achieve the required response time. 8.
When the output is short-circuited, the control circuit cannot avoid the increase of the output current. Even if the Q1FET is turned off, the output short circuit will have no effect. When the transient change of the input voltage causes the increase of the input voltage to be greater than the LED series voltage, the excessive surge current may cause damage to the LED.
Figure 1 Boost Converter LED Driver
■Boost circuit operation mode
The boost circuit can operate in two modes, continuous conduction mode (CCM) or discontinuous conduction mode (DCM), which are determined by the waveform of the inductor current. Figure 2a shows the inductor current waveform of the CCM boost circuit, and Figure 2b shows the inductor current waveform of the DCM boost circuit.
The CCM boost circuit is used when the maximum boost ratio (ratio of output voltage to input voltage) is less than or equal to 6 and the input current is greater than 1 ampere. If a larger boost ratio is required, the DCM mode must be used. However, the DCM mode will generate a larger peak current, which will increase the damage of the inductor and also cause an increase in the root mean square current. Therefore, the efficiency of the DCM boost circuit is lower than that of the CCM boost circuit, which also limits the output power of the DCM.
Figure 2 Continuous conduction mode and discontinuous conduction mode of boost circuit
■ Design of boost LED driver circuit using Supertex HV9911 as an example
HV9911 is a Close Loop, Peak Current Control, Switching Mode LED driver power control IC. It has many built-in functions to overcome the shortcomings of the boost circuit. HV9911 includes a 9-250VDC input voltage regulator. It does not require an additional power supply, and only a single input voltage provides the working power for the IC. It has a built-in 2% precision reference voltage (full temperature range) to accurately control the LED series current. It also includes a FET drive circuit for disconnection. When the output is short-circuited or over-voltage occurs, the LED string will automatically disconnect the ground path. This function shortens the response time of the control circuit (please refer to the PWM dimming circuit description). (Figure 3)
■HV9911 control circuit function
Figure 3 HV9911 internal circuit structure
The IC provides a voltage regulator circuit with an input voltage of 9∼250V, which can output a voltage of 7.75V for internal power supply of the IC. If the input voltage range is increased, an external 200V, 2W Zener Diode can be connected between the input voltage and the Vin pin of the IC (as shown in Figure 1-4). This can increase the input voltage range to 450VDC and also disperse part of the power loss generated by the internal voltage regulator circuit of the IC to the Zener Diode.
Figure 4 Increasing the Input Voltage Rating
The VDD pin operating voltage of the IC can be increased (if necessary) by connecting it to an external voltage through a diode. This diode is to prevent the IC from burning out if the external voltage is lower than the output voltage of the IC's internal voltage regulator circuit. The maximum external static stable voltage is 12V (the transient voltage is 13.5V), so a voltage source of 11V+/-5% is the ideal external boost voltage value.
The IC provides a 1.25% and 2% precision reference voltage inside. This reference voltage can be used to set the current reference level and the input current limit level. This reference voltage also provides overvoltage protection set inside the IC.
Oscillator Circuit Time Mode
The oscillation frequency of the oscillation circuit can be set by an external resistor. If this resistor is connected across the RT and GND pins, the IC operates in a fixed frequency mode. In addition, if the resistor is connected across the RT and GATE pins, the IC operates in a fixed off time mode (this mode does not require slope compensation control to stabilize the circuit). The fixed frequency time or off time can be set between 2.8ms and 40ms, and can be set using the calculation formula in the IC specification.
In the fixed frequency operation mode, all SYNCs are connected together, and multiple ICs can operate at a single frequency. In a few cases, a large resistor of 2300 must be added between SYNC and GND to suppress the ringing caused by stray capacitance. When all SYNCs are connected together, it is recommended to use a resistor with the same resistance value connected between RT and GND of each IC.
The closed loop control is formed by connecting the output current signal to the FDBK pin, connecting the current reference level to the IREF pin, and connecting the compensation network to the Comp pin (the output of the conduction operational amplifier), as shown in Figure 5. The output of the amplifier is controlled by the PWM dimming signal. When the PWM dimming signal is High, the input of the amplifier is connected to the compensation network. When the PWM dimming signal is Low, the output of the amplifier and the compensation network are cut off, so the capacitor voltage in the compensation network is maintained until the PWM dimming signal returns to the High level again, and the compensation network is connected to the output of the amplifier again. This ensures that the circuit operates normally and obtains a very good PWM dimming response without the need to design a fast control circuit.
Figure 5 Feedback Compensation
FAULT signal protection drive circuit
FAULT signal pin can be used to drive external disconnect FET (Figure 6) When IC starts, FAULT signal maintains Low potential. After IC starts, this pin is pulled high, which connects the LED in the internal circuit to the boost circuit. The circuit completes startup and lights up the LED. If there is an overvoltage or short circuit at the output, the internal circuit will pull the FAULT signal Low and disconnect the LED from the boost circuit.
FAULT signal is also controlled by PWM dimming control signal. When PWM dimming signal is Low, FAULT signal is also Low, but when PWM dimming signal is High, FAULT signal is not necessarily High. When
disconnecting LED, it can ensure that the output capacitor will not charge and discharge with the cycle of PWM dimming signal.
PWM dimming signal to FAULT signal and the output of protection circuit are connected by AND to ensure that the protection circuit can cover the input of PWM and dimming control when it is activated.
Figure 6 Disconnect FET
The working principle of output short circuit protection is that when the output detection current (at FDBK pin) is greater than 2 times the reference current setting level (at IREF pin), the protection action will occur. The working principle of overvoltage protection is that when the voltage of OVP pin is greater than 1.25V, the protection action will also occur. The two signals are sent to an OR gate and then to the protection latch circuit. When any protection action occurs, the latch circuit will turn off the GATE and FAULT pins at the same time. Once a protection action occurs, the power must be turned off and on again to reset the latch circuit.
The following two points should be noted when starting the IC:
● When VDD and PWMD pins are connected together and started by connecting or disconnecting the input voltage on the circuit, the capacitor connected to the IREF pin must use 0.1uF, and the capacitor connected to the V00 pin must be less than 1uF to ensure proper startup.
● If the circuit is started or shut down using an external signal, and the input voltage is always kept open, the capacitor value used for IREF and VDD can be increased.
Linear dimming capability
Adjusting the voltage level of the IREF pin can achieve linear adjustment of the output current. The method is to connect a variable resistor or a voltage divider resistor network or an external reference voltage to the IREF pin. However, it should be noted that once the voltage of IREF is very low, the error voltage (OFFSET) of the IC's short-circuit current protection comparator may cause the short-circuit protection to malfunction. At this time, the IC power supply must be turned off and restarted to restart the circuit. In order to avoid this malfunction, the minimum voltage of IREF is 20∼30mV.
PWM dimming (pulse width modulation dimming) capability
The PWM dimming function inside the HV9910 can achieve a very fast PWM dimming response, overcoming the disadvantage that the traditional boost circuit cannot achieve very fast PWM dimming.
PWMD controls three points inside the IC:
●GATE signal to the switch FET
●FAULT signal to the disconnect FET
●Operational amplifier to the output of the compensation network
When the PWMD signal is High, the GATE signal and FAULT can be activated, and the output of the operational amplifier is connected to the compensation network, which allows the boost circuit to operate normally.
When the PWMD signal is Low, the GATE signal and FAULT are stopped, and energy cannot be transferred from the input to the output. However, in order to prevent the output capacitor from discharging to the LED, the LED current fall time is prolonged.
This discharge capacitor will also prolong the LED current rise time when the circuit is reconnected. Therefore, it is very important to prevent the discharge of the output capacitor. The IC output FAULT signal disconnects the FET, causing the LED current to drop to zero current almost immediately. Therefore, the output capacitor is not discharged, so when the PWMD signal returns to the High level, the output capacitor does not need additional charging current, which makes the rise time very fast.
When the PWMD signal is Low, the output current drops to zero, which makes the feedback amplifier see a large error signal at the amplifier input, causing the voltage on the capacitor of the compensation loop to rise to the highest potential. Therefore, when the PWMD signal returns to High, the excessive compensation loop voltage will control the inductor peak current, causing a large output surge current to occur on the LED.
Such a large LED current is fed back with the speed of the control loop, which will extend the stabilization time. When the PWMD signal is Low, disconnecting the operational amplifier and the compensation loop helps to maintain the voltage of the compensation loop unchanged. Therefore, when the PWMD signal returns to High, the circuit immediately returns to a steady state without generating excessive LED current.
■ Design of closed-loop control circuit
The compensation loop can be used to stabilize the operation of the boost circuit. Type-Ⅰ compensation (a simple integrator circuit) or Type-Ⅱ compensation (an integrator circuit and additional pole-zero point) can be selected. The type of compensation depends on the phase of the crossover frequency of the power stage.
The loop gain of the closed-loop system (Figure 7) is given by:
(Equation 1)
Gm is the gain of the op amp (435mA/V)
Zs(s) is the impedance of the compensation network
Gp(s) is the transfer function of the power stage
Please note that although the resistor divider ratio is 1:14, the overall effect including the voltage drop of the diode will be 1:15.
Figure 7 Loop Gain of the Boost Controller
■Chip compensation network control
Assume that Fc is the crossover frequency of the loop gain, and the amplitude and phase angle of the power stage transfer function at this frequency are Aps and Φps, and the phase angle required to increase the phase margin Φm is Φboost.
(Formula 2) Φboost=Φm-Φpx-90º
Based on the required increase in phase angle, determine what type of compensation network is needed.
(Formula 3)
Φboost≦0º→TypeⅠcontrol
0º≦Φboost≦90º→TypeⅡcontrol
90º≦Φboost≦180º→TypeⅢcontrol
The HV9911-based LDE boost drive circuit usually does not require TypeⅢcontrol, so this article does not discuss Ⅲcontrol. For the use of HV9911 TypeⅠand TypeⅡcontrol, please refer to Table 1.
Table 1 Network Compensation
The design of Type Ⅰ control is quite simple. You only need to adjust Cc because the amplitude of the loop gain at the crossover frequency is 1.
(Formula 4) Rs•Gm•(2πfcCc)•1/15•1/Rcs•Aps=1
From the above equation, if the other parameter values are known, the capacitance value of Cc can be calculated.
The equations for Type Ⅱ control need to be designed as follows:
(Formula 5) K=tan(45?+Φboost/2)
(Formula 6) ωz=1/RzCz=2πfc/K
(Formula 7) ωp=Cz+cZ=(2πfc)•K
The equation for the loop gain of the crossover rate to be 1 is as follows:
(Equation 8)
Solving equations (1-6) and (1-8) at the same time can calculate the values of Rz, Cz and Cc.
■Use the chip to design the drive circuit
Table 2 Drive circuit design parameter table
Figure 8 Driving circuit design reference
Step 1: Select the switching frequency (fs)
For low voltage applications (output voltage <100V), medium power output (<30w), the switching frequency is set to 200kHz (time period is 5ms), which is a good compromise for switching losses and the size of external parts. For higher voltage applications or higher output power, the switching frequency must be reduced to consider the power loss of the external switching FET.
Step 2: Calculate the maximum switching period (Dmax)
The maximum switching period can be calculated using the following equation:
(Equation 9)
Note: If Dmax>0.85, the boost ratio is too large, and the boost circuit cannot operate in continuous conduction mode but will operate in discontinuous conduction mode to achieve the required boost ratio.
Step 3 Calculate the maximum inductor current (Iinmax)
The maximum inductor current is (Formula 10)
Step 4 Calculate the input inductance (L1).
The input inductance can be calculated based on the inductor current of 25% under the lowest input voltage operation, as shown in the following formula
(Formula 11):
Select the standard inductance of 220uH. To achieve an efficiency of 90% when operating at the lowest input voltage, the inductor loss is approximately 2-3% of the total output power. Use 3% to calculate the inductor loss.
(Formula 12) Pind = 0.03 • Voman • Iove = 0.84w
Assuming that 80% - 20% are the copper loss and iron loss of the inductor, the equivalent DC resistance of the inductor must be less than
(Formula 13)
The saturation current of the inductor must be at least 20% greater than the maximum inductor current.
(Formula 14)
Therefore, the inductor is 220uH, the DCR value is about 0.3Ω, and the inductor saturation current needs to be greater than 2A. However, it must be noted that the effective current of the inductor is equal to Iinmax (although it may not meet the efficiency requirements), but acceptable results can still be obtained.
Step 5 Select the switch FET (Q1)
The maximum voltage across the FET is equal to the output voltage. Use a 20% margin to calculate the maximum surge voltage. The FET withstand voltage is selected as:
(Formula 15) VFET=1.2Vomax=96V
The effective current flowing through the FET is:
(Formula 16) IFET∼Iimax•√Dmax=1.3A
In order to obtain the optimal design, the FET current specification must be at least 3 times greater than the FET effective current value to operate with the lowest gate charge (Qg). When using HV9911, it is recommended that the FET Qg be less than 25nC. The FET specifications currently used in this case are 100V, 4.5A, and 11nC.
Step 6 Select the switching diode (D1).
The withstand voltage specification of the diode is the same as that of the switching FET (Q1). The average current flowing through the diode is equal to the maximum output current (350mA). Although the average current of the diode is only 350mA, the diode carries the maximum input current IINmax for a short period of time. The voltage across the diode must correspond to the instantaneous current rather than the average current. Assuming that there is a 1% power loss in the diode, the voltage drop across the diode must be less than:
(Formula 17)
It is best to choose a Schottky diode. When the output voltage is less than 100V, it does not need to consider the loss of reverse recovery. Therefore, a 100V, 1A Schottky diode is selected in this case. Its forward pass voltage is 0.8V at IINmax.
Step 7: Select the output capacitor (Co).
The capacitance value of the output capacitor depends on the dynamic resistance of the LED, the ripple current of the LED string and the LED current. In the design using HV9911, a larger output capacitor (lower ripple output current) will obtain better PWM dimming results. The output of the boost circuit is simplified as shown in Figure 9a. The LED is connected in series with a dynamic impedance with a constant voltage load. The output impedance (the parallel combination of RLED and Co) is driven by the diode current Idiode. The steady-state capacitor current waveform is shown in Figure 9b.
Figure 9 Output of the boost circuit
Using the 10% peak-to-peak ripple current given in the design parameter table, the output ripple voltage is calculated as:
Step 8 Select the cut-off FET (Q2).
The cut-off FET must have the same withstand voltage specification as Q1. The conduction impedance (RON, 25C) at room temperature is selected so that the power loss of Q2 is 1% at full load output.
(Formula 22)
Step 9: Select the input capacitor (CIN).
The input capacitor is a very important component in closed-loop control. It is an important item to maintain stability. Unfortunately, the design of the input capacitor is quite complicated. To design this capacitor, you must first find the maximum inductance from the input power supply to the input end of the boost circuit, LSOURCEMAX (the sum of the two inductance values in Figure 9a) and the maximum and minimum values of the power supply resistance RSOURCe (the sum of the two resistance values in Figure 9b). This will determine the characteristics of the boost circuit. The inductance and resistance of the power supply represent the impedance of the wire connecting the input power supply and the boost circuit. In order to design the input capacitor, these two parameter values must be reasonably calculated, and these two parameter values are also related to the stability of the boost circuit. (Figure 10)
Assuming LSOURCE MAX = 1μh (this is the estimated inductance of the 1-foot 22AWG wire connecting the input power supply and the boost circuit), the next step is to select an LC resonant frequency fLC. First set fLC = 0.4fs = 80kHz, then the minimum value of the input circuit is calculated as:
(Formula 23)
(Formula 24)
(Formula 25)
(Formula 26) RSOURCE MAX = (1-Dmax) 2. RLED = 1.25
From the above two equations, it can be seen that the maximum power supply resistance value is independent of the input filter parameters, so it cannot be controlled.
However, the minimum power supply resistance value is related to the input filter parameters. The minimum power supply resistance value is calculated to be 2μΩ, which is a very small value and very easy to achieve, but in some cases, the minimum power supply resistance value of the wire is greater than the desired value. In such cases, a small resistor is added to the wire (to provide the necessary damping) or the resonant frequency of the LC must be reduced to a calculated minimum power supply resistance lower than the desired value. One thing that must be noted is that twisting the two input wires together can significantly reduce the power supply inductance value.
■Control loop design
Step 10 Select the oscillation resistor (RT)
The calculation formula for the oscillation resistor is:
(Formula 27)
Step 11: Select two current sensing resistors (RCS and RS).
The power consumption of the output current sensing resistor must be less than 0.15W, so a 1/4W resistor can be selected.
(Formula 28)
(Formula 29)
Step 12: Select the reference current setting voltage divider resistor (Rr1, Rr2).
The voltage setting of the reference current IREF can be divided by the two resistors Rr1 and Rr2 from the reference voltage inside the IC or the voltage provided externally.
(Formula 30)
Step 13: Set the slope compensation resistor (Rslope, Rsc)
Because the boost circuit is designed for fixed frequency operation, slope compensation must be used to ensure circuit stability. The slope of the added current sensing signal must be half of the maximum down slope of the inductor current to ensure that the peak current control method can operate stably under any circumstances. This can be achieved by using two resistors Rslope, Rsc to achieve the slope compensation function.
In this example, the maximum down slope of the inductor current is:
(Formula 32)
It must be noted here that the maximum output current of SCpin is 100uA, so the minimum value of Rslope is recommended to be 25kΩ∼50kΩ.
Step 14 Select the inductor current limiting resistor (RL1, RL2)
The current of the inductor is limited by two factors, the maximum inductor current and the slope compensation signal added to the inductor. Set the CLIM level from REF through two voltage divider resistors.
(Formula 35)
(Formula 36)
Step 15 Select bypass capacitor (CREF.Cpo)
It is recommended to add bypass capacitors to REF and VDD pins. It is generally recommended to add 1uF ceramic capacitors to VDDpin. If the FETQg used is > 15nC, the capacitor must be increased to 2.2uF. It is generally recommended to add 0.1=uf ceramic capacitors to REF pin.
Step 16 Select the setting of overvoltage protection point (Rovp1.Rovp2)
The overvoltage protection point is usually set 15% higher than the maximum steady-state output voltage.
(Formula 37) Vopem. 1.15. Vomax=92V
Therefore, the setting resistance can be obtained from the following two formulas:
(Formula 38)
Step 17 Design the compensation network
For a continuous current mode boost circuit and peak current control, for a switching frequency less than one tenth, the transfer function of the power stage is as follows: Formula 40)
|Gps (s) |fc = 2kHz = Φps = -80°
To obtain a phase margin of approximately Φm = 45°, the phase margin range is usually recommended to be 45°–60°, and the phase angle must be increased.
(Formula 42) Φboost = Φm-Φps-90 = 35°
From (Formula 3), it can be seen that Type II compensation is required to stabilize the system. The value of the compensation network can be calculated using (Formula 5) and (Formula 8).
(Formula 43)
(Formula 45)
From (Formula 46) Cz + Cc = 10nF, (Formula 47) Cz / Cc = 10nF, substitute (Formula 44) (Formula 47) into (Formula 45), we can get:
(Formula 48) Cc = (Cz + Cc) * Wz) / Wp = 2.84nF
From (Formula 48) and (Formula 46) we can get:
(Formula 49) Cz = 7.43nF
From (Formula 44) and (Formula 49) we can get:
(Formula 50) Rz = 1 / (WzCz) = 20.37KΩ
Select Cc = 2.2nF, 50V, COG capacitor
Cz = 6.8nF, 50V, COG capacitor
Rz = 20.0k, 1/8W, 1% resistor
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