High voltage metal oxide semiconductor field effect transistor ( MOSFET ) technology has undergone a great change in the past few years, which has provided power supply engineers with many choices. Understanding the subtle differences between different MOSFET devices and the stresses of different switching circuits can help engineers avoid many problems and maximize efficiency. Experience has shown that replacing old MOSFETs with newer MOSFET devices can achieve higher current strength and faster switching speeds, as well as other superior performance , beyond the simple difference in on-resistance .
technology
High-voltage MOSFET devices use two basic processes: one is the more conventional planar process; the other is the new charge-balanced process. The planar process is very stable and durable, but when the active area and the breakdown voltage are constant, the on-resistance is much higher than the charge-balanced process of super FET or super MOS .
For a given on-resistance, significant changes in the size of the active area can affect the device's thermal resistance and switching speed through the output capacitance and gate charge. Figure 1 shows the on-resistance of the three processes.
Figure 1 Comparison of three FET processes
Under the same breakdown voltage and size conditions, the on-resistance of the latest charge-balanced devices is only 25% of that of traditional MOSFET devices. If you only focus on the on-resistance, you may mistakenly think that you can use a MOSFET device that is one-quarter the size of a traditional device. However, due to the smaller substrate size, its thermal resistance is higher.
This has further implications when you realize that a MOSFET is not just the active area characterized by on-resistance. The so-called "edge termination" is to keep the device from voltage breakdown at the edge of the substrate. For smaller MOSFET devices, especially for high voltage devices, this edge area can be larger than the active area, as shown in Figure 2. The edge area is not good for on-resistance, but good for thermal resistance (junction to case). Therefore, having a very small active area does not significantly reduce the overall cost of the device under higher on-resistance conditions.
Figure 2 For smaller MOSFET devices, the edge area can even be larger than the active area
Key Parameters
Junction temperature (Ti) is a critical parameter for any semiconductor device. Once the device's Ti(max) is exceeded, the device will fail. At higher junction temperatures, the on-resistance is higher and the body
diode
's reverse recovery time is poor, resulting in higher power losses, so keeping Ti low helps the system operate more efficiently. It is helpful to understand the factors that influence this phenomenon and be able to calculate the junction temperature. The junction temperature can be calculated using equation (1):
Tj=Ta Pd•RΦJA(1)
There are three factors: ambient temperature Ta, power dissipation Pd and junction-to-ambient thermal resistance. Pd includes the conduction loss and switching loss of the device. This can be calculated by formula 2:
Pd=D.RDS(on).ID2 fsw.(Eon Eoff)(2)
The first term specifies the conduction losses, where D is the duty cycle, ID is the drain current , and RDS(on) is the drain-to-source resistance , which is also a function of current and temperature. The data sheet should be consulted for specific values of the junction temperature and drain current conditions for the application's operating environment.
It is usually difficult to get the specific values of D, ID and RDS(on), so engineers tend to choose the upper limit of reasonable values. Some people may think that only one parameter RDS(on) needs to be considered, but in order to get a lower RDS(on), a larger substrate is usually required, which will affect the switching loss and the recovery of the body diode .
Switching loss
The second part of the power loss formula is related to switching losses. This representation is more common with insulated gate transistors ( IGBTs ), but fsw. (Eon Eoff) better describes the power losses. At different currents, there may be no conduction losses or very low conduction losses.
These losses are affected by the switching speed and the recovery diode. In planar MOSFET devices, it is easier to control the performance of the body diode by improving the lifetime than in charge-balanced devices. Therefore, if your application requires body diode conduction in the MOSFET, for example, uninterruptible power supplies (UPS) for motor drives or some ballast applications, improved body diode characteristics can be more effective than the lowest on-resistance.
Multiply these losses by the switching frequency (fsw). Designing for the proper gate drive current is key, and input capacitance is an important factor in this design.
Thermal resistance
Another key to calculating the maximum junction temperature is the junction-to-ambient thermal resistance RΦJA, which is calculated by equation (3).
RΦJA=RΦJC RΦCS RΦSA(3)
RΦJC is the junction-to-case thermal resistance, which is related to the substrate size. RΦCS is the case-to-sink thermal resistance, which is related to the thermal interface and electrical isolation and is a user parameter. RΦSA is the sink-to-ambient thermal resistance, which is basic heat dissipation and air flow.
Semiconductor data sheets typically provide junction - to-case and junction-to-sink thermal resistances for discrete packages. Junction-to-ambient thermal resistances are often provided, but this assumes no heat losses and that the device is mounted on a board in still air, or for some surface mount devices, on a circuit board with a defined copper footprint. In most cases, the power supply engineer is responsible for determining the case-to-sink and sink-to-ambient thermal resistances .
The importance of thermal resistance is reflected in many aspects, including the rated current of the device , as shown in Table 1. The three different 600V devices given have a rated current of 7A, but their RDS(on) values and RΦJC values are very different. Since the rated current of the MOSFET device is determined only by the conduction loss formula, the impact of low thermal resistance is obvious.
So choosing the right device really depends on how you plan to use the device, what switching frequency you plan to use, what topology and thermal paths are in the application, and of course, the cost you are willing to accept.
Some general guidance is that in power factor correction (PFC) and flyback applications where there are no body diode recovery losses, if RDS(on) is greater than 1Ω, advanced planar processes such as UniFET (II), QFET and CFET are better solutions. This is largely because the lower RΦJC helps keep the device cooler. For high RDS(on) requirements, the active area of the charge reflective device is a relatively small proportion of the total substrate area due to edge termination, and planar MOSFETs are cheaper processes even if the silicon wafer is slightly larger, and the packaging cost of the two is roughly the same.
For applications that require reverse recovery, it is important to examine the diode characteristics in addition to the RDS(on) value and RΦJC value. MOSFET devices using advanced planar processes and charge-balanced processes can have improved body diode characteristics.
In applications that require the lowest RDS(on) and fast switching, new balanced devices, such as Supre
MOS
and SuperFET, can provide the greatest advantage. Generally speaking, SuperFET devices have the greatest advantage when the RDS(on) requirement is 0.5 to 1Ω. SuperMOS has a significant advantage when the RDS(on) is less than 0.5Ω. This difference is due to the effect of thermal resistance.
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