PSRR and Noise of Regulators in RF Circuits

LDO is a micro-power low-dropout linear regulator with extremely low self-noise and high power supply rejection ratio (PSRR). The SGM2007 high-performance low-dropout linear regulator has an output noise of 30µV (RMS) in the frequency range of 10Hz to 100kHz, and a power supply rejection ratio (PSRR) of up to 73dB at a frequency of 1kHz. It can provide low noise, power supply ripple rejection ratio (PSRR) and fast transient response for powering noise-sensitive analog circuits such as radio frequency (RF) receivers and transmitters, voltage-controlled oscillators (VCOs) and audio amplifiers. Its enable circuit is compatible with TTL levels and is suitable for powering digital circuits. The input voltage of SGM2007 is between 2.5V and 5.5V, which is suitable for Bluetooth digital cameras and personal digital assistants (PDAs), as well as single lithium battery-powered or fixed 3.3V and 5V systems such as wireless and high-end audio products.

The structure of the LDO low-dropout linear regulator mainly includes a startup circuit, a constant current source bias unit, an enable circuit, an adjustment element, a reference source, an error amplifier, an anti-resistance network, a protection circuit, etc. The basic working principle is as follows: when the system is powered on and the enable pin is at a high level, the circuit starts to start, the constant current source circuit provides a bias for the entire circuit, the reference source voltage is quickly established, and the output continues to rise with the input. When the output is about to reach the specified value, the output feedback voltage obtained by the feedback network is also close to the reference voltage value. At this time, the error amplifier amplifies the small error signal between the output feedback voltage and the reference voltage, and then amplifies it to the output through the adjustment tube, thereby forming a negative feedback, ensuring that the output voltage is stable at the specified value; similarly, if the input voltage changes or the output current changes, this closed loop will keep the output voltage unchanged, that is:

Vout=（R1+R2）/R2*Vref

Powersupplyripplerejectionratio(PSRR) is an AC parameter that reflects the LDO output's suppression of input ripple, and the output and input frequencies are the same. Unlike noise (Nosie), noise is generally the mean square value of its output noise voltage under a certain input voltage within the frequency range of 10Hz to 100kHz. The unit of PSRR is dB.

PSRR=20log (△vin/△vout)

Most cellular phone baseband chipsets require three sets of power supplies: internal digital circuits, analog circuits, and peripheral interface circuits. The typical value of the digital circuit power supply voltage of the baseband processor (BB) is 1.8V to 2.6V. Generally, the phone will be turned off when the Li+ battery voltage drops to 3.2V-3.3V. For the LDO that powers the baseband processor, there is at least a 500 to 600mV voltage difference, so the voltage difference requirement is not high. In addition, the digital circuit itself does not have high requirements for the output noise and PSRR of the LDO, but requires the LDO to have extremely low quiescent current under light load conditions.

The typical value of the power supply voltage of the analog circuit inside the baseband processor is 2.4V to 3.0V, and the voltage difference is 200mV to 600mV. The LDO is required to have a high low-frequency (217Hz for GSM phones) ripple suppression capability to eliminate the battery voltage ripple generated by the RF power amplifier. The LDO always maintains an effective working state and also requires a low quiescent current indicator.

The RF circuit is divided into two parts: receiving and transmitting. The typical supply voltage is 2.6V to 3.0V. Among them, the low noise amplifier (LNA), mixer, phase-locked loop (PLL), voltage-controlled oscillator (VCO) and intermediate frequency (IF) circuit require low noise and high PSRR LDO. In practical applications, the performance of VCO and PLL circuits directly affects the indicators of RF circuits, such as the purity of the transmission spectrum, the selectivity of the receiver, the noise of the analog transceiver, and the phase error of the digital circuit. Noise will change the phase-frequency and amplitude-frequency characteristics of the oscillator. At the same time, the oscillator loop will further amplify the noise and may modulate the carrier. The output noise of the LDO is affected by its internal design and external bypass and compensation circuits. The figure is a simple block diagram of a linear regulator. The main source of LDO output noise is the reference. In


order to reduce the reference noise, it is used to connect the reference bypass capacitor. Increasing the bypass capacitor can make the reference noise a secondary factor in generating the LDO output noise, which is beneficial to reducing the output noise. The typical value of the recommended ceramic capacitor is 470pF to 0.01µF. Capacitors outside this range can also be used, but they will affect the speed at which the LDO output voltage rises when the input power is turned on. The larger the bypass capacitor value, the slower the output voltage rise rate. Pay attention to this when using it.

Other factors that affect the LDO output noise include: LDO internal poles, zeros and output poles. Increasing the output capacitor capacity or reducing the output load will help reduce high-frequency output noise. The figure shows the effect of bypass capacitors on SG2001 output noise.


The figure shows the effect of bypass capacitors on SGM2007 PSRR .

LDOs need to add external input and output capacitors. Using large capacitors with lower ESR generally improves the power supply rejection ratio (PSRR), noise and transient performance overall. Ceramic capacitors are usually the first choice because they are low-priced and their failure mode is open circuit. In contrast, tantalum capacitors are more expensive and their failure mode is short circuit. The equivalent series resistance (ESR) of the output capacitor affects its stability. Ceramic capacitors have lower ESR, which is about 10mΩ. When using ceramic capacitors, it is recommended to use X5R and X7R dielectric materials because they have better temperature stability. The figure shows the ESR and frequency curve of X5R.


The figure shows the effect of output capacitance on PSRR. Large capacitors generally increase the power supply rejection ratio (PSRR) within a certain frequency range.

When selecting LDO for RF circuits, it is necessary to carefully compare the noise index and the power supply rejection ratio (PSRR) to ensure that the bypass capacitor, output capacitor and load conditions are consistent. New audio circuits, such as hands-free phones, game consoles, MP3 and multimedia circuits in cellular phones, may require a high current LDO of 300mA-500mA. The LDO should have low noise and high PSRR characteristics in the audio range (20Hz to 20kHz) to ensure good sound quality.