Simplified drive circuit for single positive gate drive IGBT

Currently, to prevent transient collector currents when high dV/dt is applied to an IGBT in a bridge circuit, designers typically design the IGBT to require a negative bias gate drive. However, providing a negative bias increases circuit complexity and makes it difficult to use high voltage integrated circuit (HVIC) gate drivers because these ICs are designed for grounded operation—the same as the control circuit. Therefore, it would be ideal to develop an IGBT with high dV/dt capability for use with a "single forward" gate driver. Such a device has been developed. The device was tested to compare performance with a negative bias gate drive IGBT, and superior test results were obtained under high dV/dt conditions.

To understand the dV/dt induced turn-on phenomenon, we must consider the capacitances associated with the IGBT structure. Figure 1 shows the three main IGBT parasitic capacitances: collector-to-emitter capacitance C, collector-to-gate capacitance C, and gate-to-emitter capacitance CGE.

These capacitors are very important for bridge converter design and are given in most IGBT datasheets:

Output capacitance, COES = CCE + CGC (CGE short circuit)

Input capacitance, CIES = CGC + CGE (CCE short circuit)

Reverse transfer capacitance, CRES = CGC

Figure 2 shows a typical half-bridge circuit used in most converter designs. The collector-to-gate capacitance C and the gate-to-emitter capacitance C form a dynamic voltage divider. When the high-side IGBT (Q2) turns on, the dV/dt on the emitter of the low-side IGBT (Q1) generates a positive voltage pulse on its gate. For any IGBT, the magnitude of the pulse is directly related to the gate drive circuit impedance and the actual value of dV/dt. The design of the IGBT itself is important to minimize the ratio of C and C, which can therefore reduce the magnitude of the dV/dt-induced voltage.

If the dV/dt induced voltage peak exceeds the IGBT threshold, Q1 generates collector current and produces large losses because the collector-to-emitter voltage is high.

To reduce dV/dt induced current and prevent device turn-on, the following measures can be taken:

Using a negative gate bias during turn-off can prevent the voltage peak from exceeding V, but the problem is that the drive circuit will be more complicated.

Reduce the CGC parasitic capacitance and polysilicon resistance Rg' of the IGBT.
Reduce the influence of the intrinsic JFET

Figure 3 shows a typical IGBT capacitance curve designed for reverse bias turn-off. The CRES curve (and others) show a characteristic where the capacitance remains high until V approaches 15V, then drops to a lower value. If this “plateau” characteristic is reduced or eliminated, the actual value of C can be further reduced.

This phenomenon is caused by the intrinsic JFET inside the IGBT. If the effect of the JFET can be minimized, C and C can decrease quickly as VCE increases. This can reduce the actual CRES, that is, reduce the effect of dV/dt-induced turn-on on the IGBT.

Figure 3. Parasitic capacitance vs. V for a typical IGBT that requires negative bias turn-off.

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This is a 1200V, 30A NPT IGBT. It is a Co-Pack device, configured with an anti-parallel ultra-fast soft recovery diode in a TO-247 package.The IRGP30B120KD-E is a typical IGBT with a smaller C and improved JFET. This is a 1200V, 30A NPT IGBT. It is a Co-Pack device, configured with an anti-parallel ultra-fast soft recovery diode in a TO-247 package.

Designers can achieve this by reducing the poly gate width, reducing the impact of the intrinsic JFET, and using cellular design geometry.

Two 1200V NPT IGBTs were compared: one was a device from another company that needed negative bias to turn off, and the other was an NPT single positive gate driver IRGP30B120KD-E from IR. The test results showed that when the other company's device was driven with a source resistance of 56Ω, the dV/dt induced current was very large.

Comparing the data of parasitic capacitance, the three types of capacitance of IR devices have also been reduced:

Input capacitance, CIES, is reduced by 25%
Output capacitance, COES, is reduced by 35%
Reverse transfer capacitance, CRES, is reduced by 68%

Figure 5 shows the reduced capacitance vs. V for the IR device, and the resulting smooth curve is due to the reduced JFET effect. When V = 0V, the C of the negative bias gate drive device is 1100pF, and the IRGP30B120KD-E has only 350pF. When VCE = 30V, the C of the negative bias gate drive device is 170pF, and the CRES of the IRGP30B120KD-E is 78pF. It is clear that the IRGP30B120KD-E has a very low C, so the dV/dt induced current will be very small under the same dV/dt conditions.

Figure 5 Relationship between IRGP30B120KD-E parasitic capacitance and VCE

The circuit in Figure 6 is used to compare the circuit performance of the two devices. The dV/dt induced current waveforms of the two devices are also obtained at the same dV/dt value.

Voltage rate, dV/dt = 3.0V/nsec
DC voltage, Vbus = 600V
External gate-to-emitter resistance Rg = 56Ω
Ambient temperature, TA = 125°C

Figure 7 18A peak of low-side IGBT switch voltage and dV/dt induced current of other companies’ IGBTs

Figure 8 1.9A peak of low-side IGBT switch voltage and dV/dt induced current of IRGP30B120KD-E IGBT

The reduction in dV/dt induced current clearly demonstrates the advantage of the single forward gate drive design. However, in this test, the effect of the Co-Pack diode current was not fully accounted for. In order to only show the effect of the IGBT on the overall current, we repeated the test using only the same discrete anti-parallel diode, as shown in Ice(cntrl) in Figure 9.

Figure 9. dV/dt induced current using the same discrete Co-Pack diode.

Figure 10 shows the I current of the negative biased gate driver IGBT without the IGBT. Figure 11 shows the I current of the IRGP30B120KD-E single positive gate driver. The currents in both cases are very low, 1A and 0.8A respectively.

If the diode currents of Figures 10 and 11 are subtracted from the overall IGBT/diode current, the result is

I (negative bias gate drive IGBT) = 18-1 = 17A

I（IRGP30B120KD-E）= 1.9-0.8 = 0.8A

It can be seen that the total reduction is 17:0.8 = 21:1

Under the same test conditions, when the gate voltage is 0V or a single forward gate drive, the circuit performance of IRGP30B120KD shows that the dV/dt induced turn-on current reduction ratio is 21:1. If the IGBT is driven in this way, the current is very small and the impact on power consumption is almost negligible.

Figure 12 Gate drive waveform

Using a single positive gate drive IGBT has the following advantages:

No negative bias required
Lower driver circuit cost
Higher gate noise immunity
Higher dV/dt tolerance
Compatible with IR monolithic gate drivers that cannot provide negative bias drive

Figure 13 Gate driver IC circuit with level shifter

The above design is also valid for PT and NPT IGBTs.

in conclusion:

The single positive gate drive IGBT is a huge step forward in device development. The IRGP30B120KD-E has a very low C value and its switching performance is very good under single positive gate drive conditions. The device can be turned off reliably without negative bias gate drive, even with dV/dt of 3V/ns at the collector. Compatibility with monolithic gate drivers provides a more superior and lower cost solution for bridge converters and AC motor drives. So we expect these advanced IGBTs to provide greater advantages for new IC designs.