Power devices are becoming smarter, and new progress has been made in high-efficiency power electronics technology

Innovation in technology and materials

Power transistor technology has continued to improve over time. Devices have become smaller and smaller, while power density has increased. For high-power transistors above 1 kV, bipolar structures have become the preferred choice; below 1 kV, especially at frequencies above 100 kHz, MOSFETs are more commonly used. For high-current applications above this voltage, IGBTs are the choice.

The main challenge in developing such devices is to minimize internal losses by reducing conduction losses due to on-resistance, reducing internal capacitance, and improving reverse recovery performance as switching frequencies continue to rise. Improving breakdown robustness is also very important due to higher breakdown voltage and unclamped switching characteristics (UIS).

In the past, the focus of developing low-voltage MOSFETs below 40 V was to minimize the die size under given on-resistance conditions to reduce unit cost. Therefore, the most important quality factor (Figure of Merit, FOM) is the characteristic on-resistance (RDS(ON)spec) in units of mΩ x mm2. Since the channel resistance has a large impact on the characteristic on-resistance in low-voltage FETs, the industry has focused on configuring as many FET channels as possible on the available area. Planar channels are replaced by vertical "trench gate" channels, and advanced lithography techniques are used to reduce surface dimensions.

However, the approach of reducing the trench FET pitch does not easily achieve the critical figure of merit defined as RDS(ON) x Qg(d) because the improvement in on-resistance per unit area is offset by the increase in gate charge (Qg) per unit area. Therefore, development has shifted to architectures such as trench FET (with an additional decoupled vertical field plate shielding the gate from the drain), trench LDMOS (combining the compactness of trench MOS with backside drain and the lower Qg(d) of LDMOS), and LDMOS with optimized metallization/packaging.

Although silicon-based transistors have continued to improve over the years, the limitations of silicon-based material properties indicate that other available solutions will need to be sought in the next decade. Currently, solutions using wide-bandgap materials (gallium nitride, silicon carbide and diamond) have emerged. These materials can provide better thermal characteristics, lower switching losses, and combine the advantages of more attractive low on-resistance (RDS(ON)) and high breakdown voltage (VBD) performance.

Wide-bandgap materials can also enable major breakthroughs in high-voltage applications. The critical breakdown fields of GaN and SiC are orders of magnitude higher than those of Si, and the devices released to date also have the advantage of higher thermal conductivity (about 3 times higher than Si). SiC is the material of choice for applications above 1 kV, while GaN is best suited for applications below 1 kV. However, there are still some technical hurdles to overcome, such as adding thick GaN layers on silicon to provide high voltage ratings, making enhancement mode transistors, and improving reliability. The first high-voltage GaN high electron mobility transistors (HEMTs) are expected to be available in the next few years.

Innovation in technology and materials

Power transistor technology has continued to improve over time. Devices have become smaller and smaller, while power density has increased. For high-power transistors above 1 kV, bipolar structures have become the preferred choice; below 1 kV, especially at frequencies above 100 kHz, MOSFETs are more commonly used. For high-current applications above this voltage, IGBTs are the choice.

The main challenge in developing such devices is to minimize internal losses by reducing conduction losses due to on-resistance, reducing internal capacitance, and improving reverse recovery performance as switching frequencies continue to rise. Improving breakdown robustness is also very important due to higher breakdown voltage and unclamped switching characteristics (UIS).

In the past, the focus of developing low-voltage MOSFETs below 40 V was to minimize the die size under given on-resistance conditions to reduce unit cost. Therefore, the most important quality factor (Figure of Merit, FOM) is the characteristic on-resistance (RDS(ON)spec) in units of mΩ x mm2. Since the channel resistance has a large impact on the characteristic on-resistance in low-voltage FETs, the industry has focused on configuring as many FET channels as possible on the available area. Planar channels are replaced by vertical "trench gate" channels, and advanced lithography techniques are used to reduce surface dimensions.

However, the approach of reducing the trench FET pitch does not easily achieve the critical figure of merit defined as RDS(ON) x Qg(d) because the improvement in on-resistance per unit area is offset by the increase in gate charge (Qg) per unit area. Therefore, development has shifted to architectures such as trench FET (with an additional decoupled vertical field plate shielding the gate from the drain), trench LDMOS (combining the compactness of trench MOS with backside drain and the lower Qg(d) of LDMOS), and LDMOS with optimized metallization/packaging.

Although silicon-based transistors have continued to improve over the years, the limitations of silicon-based material properties indicate that other available solutions will need to be sought in the next decade. Currently, solutions using wide-bandgap materials (gallium nitride, silicon carbide and diamond) have emerged. These materials can provide better thermal characteristics, lower switching losses, and combine the advantages of more attractive low on-resistance (RDS(ON)) and high breakdown voltage (VBD) performance.

Wide-bandgap materials can also enable major breakthroughs in high-voltage applications. The critical breakdown fields of GaN and SiC are orders of magnitude higher than those of Si, and the devices released to date also have the advantage of higher thermal conductivity (about 3 times higher than Si). SiC is the material of choice for applications above 1 kV, while GaN is best suited for applications below 1 kV. However, there are still some technical hurdles to overcome, such as adding thick GaN layers on silicon to provide high voltage ratings, making enhancement mode transistors, and improving reliability. The first high-voltage GaN high electron mobility transistors (HEMTs) are expected to be available in the next few years.

Power devices are becoming smarter

Smart power IC is a new device that integrates "intelligence" and "power" on a single chip. It is widely used in many fields including power converters, motor control, fluorescent lamp rectifiers, automatic switches, video amplifiers, bridge drive circuits, and display drivers.

China is the world's largest consumer electronics market, and the demand for various electronic products is increasing day by day, which indicates that there will be a huge market for smart power ICs.

Smart power ICs use a combined bipolar/CMOS/DMOS (BCD) process to enable analog, digital, and power system designs to be integrated on a single substrate. Subsequent BCD processes have improved high-voltage isolation, digital feature size (providing higher analog accuracy, logic speed and density, etc.), and power handling capabilities. Modern processes can integrate digital processors, RAM/ROM memory, embedded memory, and power drivers. For example, the BCD process can integrate power, logic, and analog functions on a single chip.

As CMOS geometry continues to shrink, the need for highly embedded intelligence has led to the integration of 16/32-bit processors, multi-Mb ROM/RAM/non-volatile memory, and complex IP. Analog functions are also increasing due to the need for higher-precision sensing mechanisms, high-bit-rate data conversion, different interface protocols, pre-driver/control loops, and precise on-chip voltage/current references for modules. The industry has introduced power drivers with 100 to 200 V and 5 to 10 A. These devices have low on-resistance and high-density, rugged high-voltage isolation architectures using deep trench and silicon-on-insulator (SOI) technology.

Integrated 600 V transistor technology for AC-DC inverters complements technology for sub-100 V applications and is proving to be another important market. Advanced submicron CMOS processes will drive the integration of low-cost, low on-resistance drivers from traditional LDMOS devices to dual and triple low surface field (RESURF) DMOS, super junction LDMOS and LIGBT. [ View related topics on this site: Application of power devices in green energy-saving design [IGBT, MOSFET] ]

Unlimited potential of packaging technology

The main trend in power semiconductor packaging is to enhance interconnection, including wafer-level technologies to reduce impedance/parasitic effects and enhanced on-chip heat dissipation. Thick copper, gold or aluminum wire bonding, ribbon/package adhesion (clip bonding), and power-optimized chip-scale packaging (CSP) are also enhancing the efficiency of the resistive connection between the die and the external electrodes. Figure 1 shows the evolution of packaging technology.

Figure 1 Power packaging integration roadmap

The power module itself is a combination of power electronic devices encapsulated according to certain functional combinations. It is no exaggeration to say that it is a packaging technology. Early power modules integrated multiple thyristors/rectifiers in a single package to provide higher rated power. Major breakthroughs in the past three decades have enabled today's modules to combine power semiconductors with sensing, driving, protection and control functions. For example, the intelligent power module is an advanced hybrid integrated power component with IGBT as the core, consisting of a high-speed, low-power die (IGBT) and an optimized gate drive circuit, as well as a fast protection circuit. The IGBT die in the IPM is of high-speed type, and the drive circuit is close to the IGBT, with a small drive delay, so the IPM has a fast switching speed and low loss. The IPM integrates a real-time detection circuit that can continuously detect the IGBT current and temperature. When a severe overload or even a short circuit occurs, and the temperature is overheated, the IGBT will be softly shut down in a controlled manner, and a fault signal will be issued at the same time. In addition, the IPM also has functions such as bridge arm tube interlocking and drive power undervoltage protection. Although IPM is more expensive, it has the advantages of compact structure, high reliability and ease of use over simple IGBT due to its integrated driving and protection functions.

The direct bonded copper (DBC) technology used in the module enhances electrical performance, while ceramic substrates (such as aluminum oxide and aluminum nitride) can also improve cooling efficiency. Improvements in packaging-assembly technology have also enabled planar co-integration of several bare chips and passive components, as well as vertical stacking technology aimed at increasing system integration. "Un-packaging" technology is another interesting research area, which mechanically integrates several populated substrates without the need for housings, terminals and bases.

Continue to promote process technology advancement

Many manufacturers are actively developing new process technologies. For example, ON Semiconductor has developed a next-generation MOSFET product based on its proprietary Trench 3 process, which can be used in desktops, notebooks, and netbooks, helping to improve energy efficiency and switching performance while reducing die size.

In the next few years, ON Semiconductor will also develop GaN wafer production process/device integration process/manufacturing process/packaging process, insulating silicon wafer production process, contact/isolation trench process module, low inductance packaging, inductor and capacitor integration and other process technologies; at the same time, it will use packaging technology to achieve product innovation, achieve higher I/O density with thinner packaging and lower footprint, continuously improve packaging thermal efficiency and operating temperature range, and make more choices for die size of each package. In addition, it will also reduce material costs with thinner and larger diameter wafers and copper wire clips.