Comparison of architecture-based and process-based DFT testing approaches

The increasing average gate count of ASIC designs forces design teams to spend 20% to 50% of their development effort on test-related issues to achieve good test coverage. Although following design for test (DFT) rules is considered good practice, testing embedded RAMs, multiple clock domains, reset lines, and embedded IP will significantly impact design schedules. Even if all of the above issues are addressed, it is nearly impossible for developers to achieve 100% stuck-at fault coverage. As a result, ASIC designs are often put into production with less than 90% fault coverage, resulting in unnecessary device defectivity and board-level failures.

Process-based approach

To insert scan test structures in a design, the first step is to replace all flip-flops with scan flip-flops. Sometimes this can be done as part of the synthesis process, although it is traditionally done later in the design flow. Inserting scan flip-flops allows a greater degree of control over individual nodes in the design, thereby improving fault coverage. However, traditional scan techniques cannot fully control or observe all user nets in the design, leaving many structures untested.

The most common type of scan flip-flop contains a multiplexer in front of the data input. In test mode, this allows data to be shifted into the flip-flop; in user mode, this allows a normal logic signal to be stored.

Traditional ASIC scan testing usually requires the following steps:

1. Prepare a test clock, and the test circuit must allow the clock to be applied to all scan flip-flops.

2. During the test, all triggers are in test mode.

3. During user mode operation, all triggers are in normal operating mode.

It is worth noting that when multiplexer-based scan flip-flops are used, the multiplexer is usually inserted in the main path of the user clock so that the test clock can be passed to all flip-flops in test mode. All flip-flops will be set to test mode at the same time.

In order to achieve sufficient fault coverage and acceptable device defect rate, traditional test technology requires many DFT rules. The consequence of not following DFT rules is that many faults cannot be tested using traditional scanning methods, thus compromising the overall fault coverage.

In order to obtain reasonable sticky fault coverage, a design must usually be fully synchronous. Therefore, this becomes the first DFT rule. Unfortunately, many designs, especially those in the networking and communications fields, require multiple asynchronous clocks, which makes it impossible not to violate this rule. Moreover, in pursuit of speed, the synthesis process often produces redundant logic structures that are re-convergent, which violates the rule.

Generally accepted DFT rules include:

1. The design must be based on a common clock and remain fully synchronized.

2. During testing, the asynchronous input of the memory cell must be enabled by an external pin.

3. Only continuous library cells designed to support automatic test pattern generation (ATPG) can be used. Sometimes it is forbidden to use falling edge triggered flip-flops.

4. Gated clocks are not allowed. They must be bypassed during testing.

5. Internal three-state buses should not be used; multiplexers are preferred.

6. Combinational logic loops are not allowed; redundant logic with re-convergence is not allowed.

7. During the test, the external bus must be disabled.

8. The interfaces between various IP modules containing different test methods must be fully testable.

Automated testing

The premise of automatic testing is that if all test-related circuits are embedded in the base array, then test-related matters can be removed from the ASIC development process. The embedded automatic test circuit is not only independent of the user design, but also built before the user design is known.

Because the automatic test circuit is embedded in the infrastructure of the ASIC, it works very differently from traditional scan testing.

The scan test method used for traditional ASIC requires all scan flip-flops in the design to be in test mode at the same time, while the sequential operation mode of automatic test allows some modules to be in test mode while other modules are still in normal mode in any specific test cycle. The functional modules in the automatic test ASIC have "control" and "observation" capabilities.

By isolating individual blocks and networks, this allows developers to test the manufacturing process to fully verify the integrity of the silicon, regardless of user design and DFT rules.

To achieve this, developers also need a new type of module. The unique Q_Cell within this module contains "control" and "observation" capabilities and can be configured as combinational logic, flip-flops, or RAM. This means that all networks can be controlled, regardless of whether they represent clocks or set/resets, and regardless of whether they are part of redundant structures or combinational logic loops.

A four-input multiplexer cell (P_Cell) can be used to implement most combinational functions, or combined with a Q_Cell to implement complex functions like a full adder.

Automatic testing not only captures the states of all signals within the device simultaneously, but also restores those states so operation can begin from any specified initial condition. Memories and triggers can be preset to simulate faults or abnormal power consumption deviations. This feature is useful for diagnosing problems in the field.

Autotest is a combination of hardware and software testing that eliminates all DFT rules and always provides 100% sticky fault coverage. This coverage becomes increasingly important as quality requirements and device complexity increase. Autotest has been successfully used in more than 100 structured ASIC designs, but it can also be applied to standard cell ASIC designs.