Design of train strain test system based on DSP

The force between the wheel and the track is an important factor in evaluating the running quality of the vehicle. Whether the force between the wheel and the track can be obtained accurately and timely directly affects the calculation of parameters such as the vehicle derailment coefficient. The strain force test system is a key link in designing a ground safety monitoring platform for train running status. The test system developed in this paper using DSP chips is precisely aimed at this need.

Hardware design of test system
Overall structure of the system
The test system is based on a high-speed and high-precision DSP, which constitutes a real-time signal test processing system including analog signal preprocessing, A/D conversion, D/A conversion and other links. Its principle block diagram is shown in Figure 1.
The analog signal output by the strain sensor is initially filtered out of the high-frequency components in the signal by the RC filter network, and then converted into a digital signal after A/D conversion. The RC filter network and A/D conversion constitute the forward channel of the test system.
The central processing unit is based on TMS320VC33. This DSP is a high-precision, large-capacity, wide-power floating-point processor with a high degree of parallelization and DMA coprocessor channels. At the same time, this design also sets up a 64K×32-bit data memory and a 512K×8-bit program memory in the system, which together with the DSP constitute the storage system of the entire system.
The programmable logic (CPLD) is the hardware control core of the test system. Its main task is to control the A/D conversion and generate the chip select signal of the storage system.
The interrupt and reset subsystem not only plays the role of system reset, but also is used to determine the location of the system application. DSP loads the application program and runs it according to this system.
Interrupt, reset
Subsystem design
In this test system, DSP needs to form a system alone, so TMS320VC33 is set to microcomputer mode, at which time TMS320VC33 has the function of program booting. When the system is powered on or reset, TMS320VC33 monitors the status of the four interrupt pins, determines the address of the user program according to the BootLoader program location table, and then runs its own BootLoader program to download the user program to the specified address space. The reset circuit for implementing the system BootLoader is shown in Figure 2.
Design of the clock circuit
The clock of TMS320VC33 can be provided by an external device or by an oscillator on the board, but the external clock has high accuracy, good stability and is easy to use. Therefore, the clock mode of the 12MHz external clock CLKMD0 CLKMD1=11 is used in this design. After internal 5-times multiplication, a 60MHz system clock is generated.
Bus driver
Due to the limited driving capability of the address bus and data bus of DSP, when the load is large, the bus driver is needed to expand its load capacity to ensure the stable operation of the system. This design uses TI's wide bus 16-bit bidirectional bus driver SN74LVTH16245, which has high integration and performance.
Storage subsystem design
The main issue considered in the memory interface design is: how to use the EP2ROM+high-speed RAM configuration to implement the storage subsystem.
EP2ROM is used to store the program and initialization data of the test system. When the system is powered on, TMS320VC33 automatically loads the program and initialization data from the low-speed EP2ROM to the high-speed RAM. After loading, the program runs at full speed in the high-speed RAM. The starting address of the EP2ROM for loading programs and initialization data in the system is 400000h. At the same time, the system also expands 64K high-speed RAM, with a starting address of 100000h. In addition, the chip select signal is implemented by the CPLD in the system.
For the interface between TMS320VC33 and EP2ROM, the system uses an AM29F040 (512K×8) to implement 8-bit data width program boot. The address space occupied by EP2ROM is 400000h~47FFFFh. The waiting cycle inserted when reading EP2ROM is controlled by software.
The programs and data of TMS320VC33 during real-time operation are stored in the fast RAM, so the fast RAM and TMS320VC33 must implement a zero-wait interface. According to the timing requirements, when TMS320VC33 works at a 60MHz clock, the access speed of the fast RAM must be less than 13ns. The fast RAM used in this test system is IS61LV6416-8T, with an access speed of 8ns. Since the data width of this fast RAM is 16 bits, and the data width of TMS320VC33 is 32 bits, two chips must be used to form a 32-bit data width, and the write enable signal is connected to the decoded write signal, and the output enable signal is connected to the decoded read signal. The address space occupied by the fast RAM in the test system is 0x100000~0x110000.
Communication subsystem
In the strain test system, in order to transmit the processing results of the sampled signal by TMS320VC33 to the PC through the serial port for display or further processing, the design uses TI's TL16C550 extended asynchronous communication chip to connect the DSP to the PC to complete the communication between the test system and the PC.
In the serial communication between TL16C550 and TMS320VC33, although it can work in a query manner, this will reduce the performance of the system. This design introduces external interrupts through the RXRDY and TXRDY pins of TMS320VC33, so that the system works in interrupt mode, ensuring high-speed communication between TMS320VC33 and PC.
In addition, this test system uses the serial communication interface of TL16C550 to complete information exchange with the host PC. At this time, since the RS-232 circuit level is different from the TTL level, it must be converted. MAX232A is used in the design to complete this function.
Programmable logic device-decoding module
The decoding module in the test system is mainly used to realize the DSP to manage the off-chip memory and I/O devices, and to allocate different address spaces to the external memory and I/O devices according to the address signal provided by the DSP. For this test system, the encoding method mainly considers the interface capability of TMS320VC33. The total address space capacity of TMS320VC33 is 16M, and the use of unified addressing will not pose a great threat to the memory capacity. In addition, TMS320VC33 does not have dedicated I/O instructions and I/O port buses, so a unified encoding method is used in the test system, and the decoding circuit is designed with ABLE language.

Test system software design
The quality of the test software algorithm is directly related to the performance of the entire test system. The software flow of this test system is shown in Figure 3.
The test program first initializes the entire system. After completing the system initialization, the system is in a query state to query whether new data sampling is completed. The data sampling program is completed in the interrupt program. When the system completes an A/D conversion, it applies for an interrupt to TMS320VC33. TMS320VC33 responds to the interrupt, reads the conversion result in the interrupt service program and sets the flag: EXINT=1, notifying the main program that the sampling is completed. After querying EXINT=1, the main program processes the data, and the processing result is sent to the serial port of the PC through the parallel port of TMS320VC33 through parallel/serial conversion, and the flag EXINT is set to 0, starting the next round of sampling waiting.

Signal integrity analysis and
electromagnetic compatibility design
Considering that the system operates in a harsh environment and the electromagnetic interference of the track line is relatively strong, the design should consider issues such as signal integrity and electromagnetic compatibility.

Power supply EMI is a major factor affecting the system's anti-interference ability. A simple method is to connect a capacitor in parallel to the power supply pin of each chip for power supply filtering. Another factor that affects the system's anti-interference ability is the routing quality of the signal on the circuit board. The inductance of the printed wire should be minimized, and the wire should be as short and thick as possible. At the same time, attention should be paid to suppressing crosstalk between printed board wires and avoiding electromagnetic radiation generated when high-frequency signals pass through printed wires. In addition, attention should be paid to the reasonable arrangement of power ground, etc.

Conclusion
The train strain test system with DSP as the core proposed and designed in this paper effectively solves the technical problems in practical engineering applications, and considers the signal integrity analysis and anti-electromagnetic interference ability of the test system. It provides a good reference solution for the field of data acquisition and processing.