Design of frequency characteristic tester for electronic engineering

1 Introduction

Frequency characteristics are the most intuitive reflection of network performance. Frequency characteristics tester is a fast, convenient, dynamic and intuitive measuring instrument that measures the amplitude-frequency characteristics and phase-frequency characteristics of a network and displays the corresponding curves. It can be widely used in the field of electronic engineering.

The tester is based on the swept frequency heterodyne principle and uses the minimum system composed of a single-chip microcomputer and FPGA as the control core. It can well complete the test of the amplitude-frequency response and phase-frequency response characteristics of the active twin-T network in the frequency range of 100 Hz to 100 kHz, and realize the simultaneous display of the amplitude-frequency and phase-frequency response characteristic curves on a general digital oscilloscope.

2 System Design

2.1 Overall plan

This design uses a combination of a single-chip microcomputer and an FPGA. The scanning signal source of a sinusoidal signal with a steppable output frequency is used as the input signal Vi of the network under test, and the output signal Vo of the network under test is a frequency-steppable signal. By measuring the amplitude of each frequency point, the effective value of Vo and Vi can be obtained, and the ratio of the two is the amplitude-frequency response of the point; Vo and Vi are compared and shaped through zero, and then sent to the FPGA to measure the phase difference. The rising edge of Vi starts counting, and the rising edge of Vo stops counting. The ratio of the obtained time value to the signal period is the phase-frequency response of the point. This solution uses FPGA to measure the phase difference, and it is easy to make a DDS scanning signal source.

2.2 Design of frequency sweep signal source

The design uses a direct digital synthesis (DDS) signal source. The DDS signal source is a frequency source controlled by digital quantities, as shown in Figure 1. The specific implementation process is: the amplitude value of a complete cycle of the output waveform is quantized and stored in a dual-port RAM in a phase step order, read out at a certain address interval, converted into an analog signal by D/A, and then filtered out by a low-pass filter to remove the small steps caused by D/A conversion and the burrs generated by the digital circuit, so that a high-precision, high-purity sinusoidal signal can be obtained. Theoretically, as long as the number of bits of the accumulator is large enough, any small frequency step can be achieved, and the frequency resolution is very high, which is very close to continuous change. Precise phase adjustment can be easily achieved by presetting the initial value of the phase accumulator.

2.3 Amplitude measurement module solution

This module uses an integrated true effective value conversion device. It measures the true effective value of the measured signal and then converts it into amplitude. It can measure the amplitude of the sine wave. The hardware and software of this solution are simple, with high accuracy and ideal effect.

2.4 Phase measurement module solution

This module uses the phase-time conversion method. Two sinusoidal signals with the same frequency and different phases are shaped and XORed to generate a square wave with a pulse width of Tx and a period of T. There is always a one-to-one correspondence between the phase difference and (TX/T). Therefore, no matter how the frequency changes, as long as (Tx/T) is measured, the size of the phase difference is determined.

3 Theoretical analysis and calculation

3.1 DDS related calculations

(1) Phase-shift signal generator DDS Since the setup time of the output stage D/A converter DAC0800 is 100 ns, the clock frequency should be less than 10 MHz. Take the clock frequency fout = 8.388 608 MHz, the phase accumulator N = 23 bits, then:

(2) Frequency sweep signal DDS Due to the rich resources in the FPGA chip, in order to ensure sufficient frequency sweep accuracy, the reference clock frequency fclk is set to 40 MHz. By controlling the range of the frequency control word K, the speed requirement of DAC0800 can be fully met.

3.2 Phase measurement related calculation

The frequencies of the measured signal and the reference clock are measured by FPGA using the equal precision method as f0 and fCP respectively. After phase detection of the measured signal, the counter count is controlled by the obtained phase difference pulse width T, and its count value is set to M. Then the phase difference of the measured signal is:

(2) Phase measurement resolution calculation The frequency range of the digital phase shift signal generator is 20 Hz to 20 kHz, and the phase difference measurement range is 0 to 359°. Therefore, the counter clock frequency fclk is at least 72 MHz. Take fCP = 100 MHz. Since the counter resolution is ±1, the corresponding minimum phase resolution (when f0 = 20 kHz) is:

4 System overall block diagram

The system design takes advantage of the FPGA's stability, reliability, and programmability to allow FP-GA to achieve as many functions as possible, thereby reducing the work of the analog part and making the entire design more reliable. The overall system block diagram is shown in Figure 2.

5. Design of main functional circuits

5.1 Sweep signal output section

The double-T network sweeps the frequency, and the output signal voltage effective value is measured by AD637 and then converted into amplitude, which is sent to the oscilloscope for display. To ensure the purity of the DDS output signal, a low-pass filter composed of LF356 is added before its output, and the cut-off frequency is 300KHZ. The specific circuit is shown in Figure 3.

5.2 Oscilloscope display part

In addition to LCD display, the system can also display curves with the help of an oscilloscope. In order to display the amplitude-frequency and phase-frequency characteristic curves separately, the DC level is superimposed to display the two curves at the appropriate position of the oscilloscope screen (the upper part of the oscilloscope is the amplitude-frequency curve, and the lower part is the phase-frequency curve). According to needs, a certain curve can also be displayed independently. The amplitude and phase data are both 256 bits, and the D/A conversion is completed using DAC0800. Figure 4 is a common circuit diagram.

5.3 System Software Design

The software design is written in C and Verilog HDL languages. The former is run by the microcontroller to complete the main control functions of the system such as real-time display, key value reading, and data processing; the latter is written into the FPGA to complete keyboard scanning.

The filter module is written into it to process the waveform, and the DDS control generates the final waveform display and acts as a bridge between the microcontroller and the peripheral circuit. The system software flow is shown in Figure 5.

6 Conclusion

The system can well complete the test of the amplitude-frequency response and phase response characteristics of the active dual-T network in the frequency range of 100 Hz to 100 kHz, with a frequency stability of 10-6, and can simultaneously display the amplitude-frequency and phase-frequency response characteristic curves on a general digital oscilloscope. At the same time, the software design of the system microcontroller realizes a friendly human-computer interaction interface, giving full play to the intelligent characteristics of the microcontroller.