Higher and faster come with stronger requirements to meet the challenges of DDR5 memory verification and debugging

Practical sharing | Higher and faster with stronger requirements, meet the challenges of DDR5 memory verification and debugging

The world is experiencing an unprecedented era of explosive data growth, a trend that is expected to accelerate as new technologies are implemented on a wider scale. Typical examples include: next-generation wireless communications in the form of 5G, the ever-expanding fields of artificial intelligence and machine learning, the Internet of Things (IoT), cryptocurrency, virtual reality, and even automotive. Throughout 2021, it is expected that 44 trillion GB (440 trillion bytes) of data will be generated, and it is estimated that 1.7MB of data is generated every second for every person on the planet. Such a huge amount of data needs to be stored, accessed, and analyzed faster than ever before, which requires systems with higher bandwidth, higher storage density, and higher overall performance.

Faster memory brings new challenges to DDR5 testing

To cope with the increasing amount of data being generated, memory performance must be increased to store, transfer and process all this information. The main bottleneck in this process is the speed at which the memory can access and transfer data. Slow memory access times can cause overall system performance to slow down, and data throughput is itself limited by the transfer rate of the memory. Historically, the dominant form of high-performance, fast-access memory has been Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). DDR SDRAM was introduced as a standard in the 1990s and has evolved very rapidly since its introduction, with the fourth generation standard, DDR4, being introduced in 2014. DDR4 is a memory interface that initially transferred data at 1600 MT/s, eventually reaching 3200 MT/s as the standard matured. This was sufficient when computer processors had only 8 cores, but with the advent of today's multi-core processors with 28-64 cores (and 80-96 cores in the future), it is clear that we need memory performance that exceeds the capabilities of DDR4.

To help meet this demand, the industry is migrating from DDR4 to the next generation DDR memory standard, DDR5. DDR5 will succeed the previous generation standard and become the dominant and fast-growing standard. DDR5 will initially offer a transfer rate of 3,200 MT/s based on DDR4, with a maximum of 6,400 MT/s, and is expected to expand to up to 8,400 MT/s in the future.

DDR5 introduces a whole new set of challenges that must be overcome during implementation and verification. Higher data rates increase the required test equipment bandwidth, require new processes to measure jitter that was not previously possible, require new DDR cells in the form of receiver equalization, and even introduce new standardized tests using fixtures, all of which are significant challenges for DDR5 verification.

Solution: Tektronix Oscilloscope and TEKEXPRESS DDR TX Software

The improved performance of DDR5 means that higher performance equipment is required to analyze and test DDR5-enabled devices. To meet this performance demand, Tektronix has developed an in-depth solution that utilizes high-bandwidth oscilloscopes and probe hardware, such as the DPO71604SX and P7716, while adopting a new software automation platform.

Figure 1. Tektronix tools used in the DDR5 test solution.

Tektronix TekExpress DDR Transmitter (Tx) software is an automated test application specifically designed to validate and debug DDR5 devices according to the parameters specified in the JEDEC (Joint Electron Device Engineering Council) specification. Tektronix Option DDR5SYS (TekExpress DDR Tx) includes full test coverage and a variety of debug tools for:

DRAM components

Data buffer/RCD components

System circuit board

Embedded Systems

Server and Client/Desktop

TekExpress DDR Tx supports the measurement of more than 50 DDR5 electrical and timing parameters according to the DDR5 JEDEC specification. It has built-in powerful tools to assist in characterization and debugging, such as multi-strobe function, DDR5 DFE analysis software, and user-defined acquisition mode that allows users to fully control test conditions.

Tektronix TekExpress DDR Tx solution has a variety of unique innovative features, reducing the amount of work spent on testing and accelerating the DDR system and device test process. TekExpress DDR Tx provides a simple step-by-step operation of the easy-to-use interface to speed up the test process.

Steps taken in testing and memory circuits

Customers can use the following steps to verify whether the product meets the DDR5 specification:

1. Soldering a high impedance Tektronix probe to the DDR subsystem under test allows access to the electrical signals of interest.

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2. Tektronix TekExpress DDR Tx software analyzes the detected signal and compares it with the DDR5 specification. Other software running on the oscilloscope can be used to perform various tests, such as drawing eye diagrams and measuring relevant electrical parameters.

Figure 2 shows an example of performing system-level TX testing using a probe to access the device. In this example, the system on chip (SOC) communicates with the device under test (DRAM/RCD/DB) to transmit bidirectional traffic over the DDR bus. The user accesses the interface using an interposer soldered under the DRAM and probes the interface using a high-impedance probe amplifier. The TekExpress DDR Tx software provides the necessary tools to measure various parameters such as clock jitter, read/write timing, and even eye diagrams.

Figure 2. System-level TX testing.

3. At the end of the test, a pass/fail report is generated providing detailed information about the device under test, the physical setup, and the comparison of the parameters under test to the JEDEC specification.

4. If a metric fails the test or an unexpected result occurs, you can further use the TekExpress DDR software solution to debug the result.

DFE Receiver Equalization and Signal De-Embedding Using Tektronix SDLA64

Increasing signal speeds and shrinking form factors present several challenges for next generation multi-gigabit designs and test methods. Smaller form factors make signal access more difficult, resulting in less than ideal probing points, which in turn results in loss and reflections of the captured signal, since impedance discontinuities do not exist at ideal measurement locations.

The advent of DDR5 has made the tools previously used for DDR testing and debugging insufficient. Designs use higher data rates and more stringent loading requirements, making it difficult, if not impossible, to access signals successfully. One effective way to address these issues is to use the Tektronix Serial Data Link Analysis (SDLA) software package. The SDLA feature allows users to eliminate the loading effects of the test setup (probes, interposers, cables) through a de-embed process. Whether it is reflections, insertion losses, cross-coupling or other impairments, SDLA provides powerful capabilities to effectively analyze signals as if these effects did not exist. This can greatly improve the effectiveness and accuracy of the measurements obtained, and even directly determine whether the device passes the test.

Tektronix DFE Analysis Software

For the first time in DDR, receiver equalization was introduced in the form of 4th-tap DFE (decision feedback equalization). This brings additional challenges when accessing and analyzing DDR5 signals. For example, even after de-embedding, the generated eye diagram may still be closed (Figure 3). In order to open the eye diagram further, DFE equalization is necessary.

Tektronix has developed various tools to help address the issues that DFE introduces during the test process. Using SDLA, the continuous data stream from the device can be analyzed to train the DFE gain and tap values. The DFE characteristics can then be input into the TekExpress DDR Tx Automation software to generate an eye diagram after applying DFE on the burst signal. Alternatively, a standalone DFE application (standard with TekExpress DDR Tx) can be used, which allows the user to manually generate and view DDR signals after applying DFE equalization outside the automation framework.

Figure 3. Example of opening the eye in an eye diagram.

Jitter Noise Floor Calibration

DDR5 introduces new Rj/DJ jitter measurement requirements for CLK, DQS, and DQ. In addition, the Rj specification is about 0.5ps (very tight). Tektronix has developed a new jitter noise floor calibration technology that can be used directly on Tektronix oscilloscopes. The tool provides an option to include probes, probe tips, and de-embed filter files in the noise calibration process to account for additional generated or amplified noise. The tool is fully integrated with the oscilloscope analysis software (DPOJET) to eliminate the oscilloscope's noise jitter from the measurement results.

Summarize

As the industry moves to DDR5 development, test, and production, new hardware and software tools are required to address the latest challenges of DDR5 testing. Tektronix has developed a range of high-bandwidth oscilloscopes and probes to acquire signals from DDR5 devices, as well as powerful software tools for validation. Visit Tek.com to learn more about our solutions and watch video demonstrations or webinars related to DDR5 and Tektronix solutions.