Parallel Test Method of DC Parameters in Verigy 93000

　　In the current stage of rapid development of SoC and fierce competition in the semiconductor industry, improving test efficiency and reducing test costs are issues that practitioners need to think about and solve.

　　Verigy 93000 is a single-platform scalable test system that is a chip test system solution that meets the comprehensive integration needs of SoC technology .

　　This paper describes a test method that enables the Verigy 93000 to use hardware resources independently and in parallel when performing DC parameter tests, thereby saving test time and improving test efficiency.

　　2 Verigy 93000 Hardware Resources for DC Testing

　　2.1 PMU (parameter measure unit)

　　PMU is the most commonly used hardware resource for DC testing in Verigy 93000 (as shown in Figure 1). There are two types of PMU in the most widely used Pinscale test system. One is called PPMU (Per-Pin PMU), which is included in each digital channel. According to the configuration structure of the test system, there can be up to 2048 large heads and 1024 small heads; the other HPPMU (High Precision PMU) is one in each Group  , with 8 large heads and only 4 small heads. Therefore, in the test, as long as the parameter range and accuracy of the PPMU meet the chip requirements, we try to use PPMU as much as possible, and use the appropriate programming method to achieve full parallel use of hardware resources to speed up the test.

Figure 1 93000 PMU resources

　　2.2 Verigy 93000 DPS (Device Power Supply, chip power supply ) resources

　　Each DPS board in Verigy 93000 can provide 8 power channels. In addition to providing power to the chip, the power channels also have the function of adding voltage and measuring current, which is usually used for chip power consumption testing.

　　This article does not discuss such testing.

　　3 Test Method for Fully Parallel Use of PPMU Resources

　　PPMU is a hardware resource in every digital channel of Verigy 93000. It has two functions: voltage-to-current measurement (VFIM) and current-to-voltage measurement (IFVM). There are usually two ways to implement these two functions for DC testing.

　　1) Traditional method: This is achieved by calling the corresponding API (Programmable Application Interface ) of PPMU, PMU_VFIM (apply voltage to measure current) and PMU_IFVM (apply current to measure voltage). However, when this method is used for testing, if different pins require different test conditions, each pin is tested serially, so the advantage of the per-pin PMU resource of the machine is not fully utilized, and the test time will increase accordingly.

　　2) Flex DC test method: It can make the PINs under different conditions completely independent of each other when using PPMU to test. Therefore, when using PMU for DC testing, in order to improve test efficiency and increase output, the tester should use this method as much as possible if the test conditions allow.
 

　　The comparison of the two methods is shown in Table 1.

Table 1 Comparison of two DC test methods

　　3.1 Specific implementation of Flex DC programming method

　　The Flex DC test method is implemented in the program by creating a task list through PPMU_SETTING, PPMU_ RELAY , PPMU_MEASURE, and TASK_LIST. At this time, we need to set the PPMU working mode and condition range, RELAY status, and test result acquisition corresponding to the pins of different test conditions to the same SETTING, RELAY, and MEASURE, and then add the above settings to the same task list. In this way, for the actions contained in different pins in the above SETTING, RELAY, and MEASURE, the machine is completely independent and parallel during the test execution process, which can achieve the best utilization of resources.

　　Take 2 pins as an example. In the pin1 test, 5 V voltage needs to be applied to measure the current, and 2.5 V voltage needs to be applied to measure the current. The Flex DC code is as follows:

　　PPMU_SETTING set1；

　　PPMU_RELAY relay1；

　　PPMU_MEASURE measure1；

　　TASK_LIST task1；

　　set1. pin（ pin1 ）。 vForce（ 5 V）。iRange（ 40mA）。min（ 0 mA）。max（ 50 mA）；

　　set1.pin（ pin2 ）。vForce（ 2.5 V）。iRange（ 40mA）。min（ 0 mA）。max（ 40 mA）；

　　relay1.pin（pin1, pin2）。status（“PPMU_ON”）；

　　measure1.pin （pin1, pin2）。execMode （TM::PVAL）；

　　task1.add（set1）。add（relay1）。add（measure1）；

　　task1.execute（ ）；

　　Take a power chip as an example. Most of the test items of this chip are DC test items, plus a small part of functional test. Let's look at the comparison of test time between using Flex DC test method and directly using PPMU_IFVM for testing. (As shown in Table 2).

Table 2 Parameter comparison of two test methods for a power chip

　　The comparison in the table shows that if the test program is not optimized, the time difference is 0.6 s for single-chip testing and 0.9 s for dual-chip testing. If the test program is optimized (mainly for multi-chip testing, so that actions that can be performed in parallel in chip testing at different locations are executed simultaneously), the time difference is more obvious, 0.9 s for single chip and 1.6 s for dual chips. It can be seen that the Flex DC test method can effectively reduce the test time.

　　4 Summary

　　Combined with the characteristics of Verigy 93000 SoC tester, a method of parallel use of DC test resources is discussed. The results show that this method can fully parallel use of hardware resources in the test, effectively reducing the test time.