Design of USB sidetone ranging signal generator based on AD9957

　　With the continuous progress of my country's aerospace technology, deep space ranging technology has received more and more attention. In the deep space ranging system, the intermediate frequency signal generator is of great significance to the system performance.

　　In the USB (unified S-band) system, the transmitting module implemented by the original analog circuit has problems such as imperfect performance, small input dynamic range, poor controllability, inability to adapt to large-scale changes in center frequency, and large size. In order to solve the above problems, on a standardized universal digital modulation signal generator platform, the carrier center frequency, output power, phase modulation index, ranging tone on/off control and other parameters can be changed through peripheral control circuits.

　　With software radio as the core, the design of a general modulation signal generator based on PLD (programmable logic device) further provides the hardware design and software design ideas for realizing the intermediate frequency USB sidetone ranging signal. The simulation results and on-chip hardware data acquisition results prove the correctness of the output signal, and at the same time achieve flexible parameter controllable performance.

　　1 USB sidetone ranging principle

　　There are three types of ranging signals available in the USB system: pseudo code, side tone, and pseudo code plus side tone, forming different ranging systems. At present, the most commonly used in the microwave unified system is pure side tone ranging.

　　The USB system sidetone ranging signal is a sinusoidal phase modulated wave, which is modulated by K sinusoidal subcarriers (which can be modulated by information). In order to reduce the intermodulation interference between the modulated subcarriers, the modulation method is narrowband phase modulation. This modulated signal is expressed as: 　　Where: A is the carrier amplitude; ωc is the carrier angular frequency; mi is the phase modulation index of the i-th sinusoidal subcarrier to the carrier; Ωi is the angular frequency of the i-th sinusoidal subcarrier.

　　The USB system uses 7 sidetones, the primary sidetone is 100 kHz, and the secondary sidetones are 20 kHz, 4 kHz, 800 Hz, 160 Hz, 62 Hz, and 8 Hz; after spectrum folding, the secondary sidetones become 100 kHz, 20 kHz, 16 Hz, 16.8 Hz, 16.16 Hz, 16.032 Hz, and 16.008 Hz, which are called virtual secondary sidetones. The selection of the highest sidetone is related to the ranging accuracy requirements, and the secondary sidetones are necessary for sidetone matching and deambiguation.

　　In the pure sidetone ranging system, there are two modes: "simultaneous transmission" and "sequential transmission". We adopt the method of sending the sidetone simultaneously. In this method, the main sidetone f7 is always sent, and in the deambiguation stage, a virtual secondary sidetone is sent each time in the order of high to low sidetone frequencies. The main sidetone and the virtual secondary sidetone are matched and deambiguated layer by layer in the order of sending the sidetones, until the main sidetone is matched with the lowest sidetone, that is, the unambiguous distance measurement stage is entered. After that, only one main sidetone is sent. The sending process is shown in Figure 1. 　　2 AD9957 Function Introduction

　　AD9957 is a direct digital frequency synthesizer (DDS) integrated circuit with a built-in 14-bit D/A converter produced by Analog Devices, USA. The basic block diagram is shown in Figure 2. The 　　sampling speed of AD9957 reaches 1 GSPS (1 billion samples per second). At the same time, the power consumption is reduced by more than 50% compared with other DDS. The dynamic performance is as high as 400 MHz output frequency, and the sFDR (spurious-free dynamic range) is as high as 80 dB or more. When applied to wireless and wired systems. The real-time output of up to 400 MHz intermediate frequency provided by the AD9957 modulator or QDUC (orthogonal digital up-converter) is used to simplify data transmission. AD9957 also provides a wide parallel interface for fast programming. It has a 16-bit parallel port with an update rate of 250 MHz, allowing the 32-bit frequency control word to be updated every 8 ns. This fast programming capability allows it to be used in high-speed waveform generators, frequency hopping synthesizers, security communications, and various radar and scanning systems, etc., where extremely fast changes in frequency or phase are required.

　　In addition, AD9957 supports QDUC with output up to 400 MHz. Since AD9957 integrates high-speed DDS, 14-bit D/A converter, clock multiplication circuit and digital filter, when applied to wireless or wired communication infrastructure system, it can realize frequency conversion on baseband, making data transmission simple, low-cost and efficient. 1 GSPS NCO (numerically controlled oscillator) and D/A converter allow AD9957 to provide direct output up to 400 MHz, so there is no need to use up-conversion stage and reduce the requirements for filters.

　　The main features of AD9957 are: 32-bit phase accumulator; SPI interface with baud rate up to 2 Mb/s; built-in 1 024×32 bit RAM, which can realize internal modulation function; internal 1.8 V power supply, ultra-low power consumption; built-in low-noise reference clock multiplier allows low-cost, low-frequency external clock to be used as system clock while still providing excellent dynamic performance; supports test vector and amplitude ramp control function. 

        3 System Design and Implementation

　　The specific implementation block diagram of the system is shown in Figure 3. The hardware design mainly includes peripheral control, FPGA, AD9957 and filter amplifier circuit. 　　3.1 Peripheral control module design

　　The peripheral control module is mainly composed of a PC and corresponding peripheral control circuits, and is mainly used to control the selection of the primary and secondary side tones and the selection of the phase modulation index corresponding to the primary and secondary side tones.

　　3.2 FPGA Design

　　In this design, the FPGA (field programmable gate array) uses the XC3S200 produced by XILINX. The VHDL programming language is mainly used to write the hardware development program of the core processing module, which includes the design of three modules: clock generation module, side tone generation module and initialization module. As shown in Figure 4. 　　The clock generation module (clk_module) is mainly used to provide the unified working clock required by the system and the differential clocks Clk_P and Clk_N required by AD9957, and provide a reset signal for the system.

　　The sidetone generation module (ceyin_module) uses the DDS IP CORE provided by XILINX to directly generate the required primary sidetone and virtual secondary sidetone. By calculating the control word as the input of DDS, the sinusoidal signal output of the corresponding frequency can be obtained, which is then multiplied by the respective phase modulation indexes m1 and m2 sent by the peripheral control module and sent to the adder for addition. Finally, the two sine and cosine signals are output through the lookup table as the two input signals of AD9957.

　　The initialization module (AD9957_init) is used to generate the configuration signals of AD9957, such as the chip select signal CS, the serial port data write SDIO signal, etc. The timing simulation of serial port write data using Modelsim SE 6.0 is shown in Figure 5. 　　3.3 AD9957 Design 　　The sidetone signal in formula (2) can be orthogonally modulated with the carrier signal to obtain the required sidetone ranging signal. In the design, the QDUC mode of AD9957 is used. The I/Q two-way signal sent by the FPGA is phase-modulated with the carrier signal generated by the internal DDS of AD9957 and then output. After bandpass filtering, the required intermediate frequency (70 MHz) USB signal can be obtained. ChipScope Pro 8.2i of XILINX is used for real-time data acquisition. ChipScope Pro is an online on-chip signal analysis tool for XILINX FPGA. It reads the internal signal of FPGA online and in real time through the JTAG port.

　　The data collected by the data observation window is shown in Figure 6. 　　4 Conclusion

　　This paper presents a design of a sidetone ranging signal generator based on FPGA and AD9957. The design process makes full use of the IP CORE in FPGA to realize the functions of DDS, multiplier, adder and lookup table required in the design, which not only simplifies the implementation program but also saves resources. At the same time, through the design of the peripheral control module, flexible parameter controllable performance is achieved.

　　The intermediate frequency USB signal generator designed in this paper has been applied in a deep space ranging system.