Design of high-speed data acquisition system for B-mode ultrasonic radio frequency signals

Preface

Medical ultrasound imaging uses the difference in acoustic characteristics reflected by ultrasound waves passing through various tissues of the human body to distinguish different tissues, and displays the interface of organs and the fine structure inside tissues in the form of images. This examination method combines multiple technologies such as ultrasound physics, modern electronic technology and biomedicine. It is the fastest-growing and most widely used imaging method in medicine after X-ray imaging technology. In particular, the emergence of digital scanning converters (DSC) and digital signal processing ( DSP ) has pushed B-mode ultrasound imaging technology to a new level dominated by computer digital image processing, with strong functions, high degree of automation and good image quality.

In digital ultrasound imaging systems, the method of digital image processing directly affects the quality of imaging. In recent years, in order to improve the resolution of ultrasound images, improve the quality of images, and better extract information that is beneficial to medical diagnosis, a variety of image processing methods have been developed. According to different processing modes, they are mainly divided into two directions: (1) One type suppresses additive noise in the image or performs regional operations on the image to improve image quality. (2) Use deconvolution methods. In many image processing algorithms, the experimental image data used is image data that has undergone a series of linear and nonlinear and detection processes, and the original ultrasound RF signal has lost some information. In order to better evaluate the effectiveness of an algorithm, it is an ideal choice to use the original data directly quantized from the RF signal of the B-type ultrasound system. However, at this stage, most medical

The image data provided by the ultrasonic imaging system are all processed by detection and other methods. Therefore, it is necessary to design a data acquisition card to obtain image data directly quantified from the radio frequency signal.

1 System Design

The experimental object of the data acquisition card designed in this experiment is Belson 200AB ultrasonic diagnostic instrument. It is a portable electronic convex array scanning B-ultrasound, with a main frequency of 3.5MHz, 2.5MHz~5MHz frequency conversion, 80 basic elements R60 convex array probe, probe width: 3.84cm, detection depth: ≥170mm, scanning range: 100mm×210mm, 256 grayscales, resolution: horizontal ≤2mm vertical ≤1mm, scanning lines: 512 lines/frame, frame rate: 30 frames/second.

The principle block diagram of the receiving and display part of the Belson 200AB ultrasonic diagnostic instrument is shown in Figure 1. In this figure, the radio frequency echo signal of the B-type ultrasound is processed by a series of processes such as pre-launching, focusing, differential amplification, time gain compensation, and detection, and finally the ultrasonic image is sent to the monitor for display and storage and printing through digital processing. According to the requirements of the original data, the radio frequency signal input source of the data acquisition card comes from the radio frequency signal before the DF/TGC amplification module in Figure 1.

The system design includes hardware and software. The hardware part is based on the computer PCI (peripheral component interconnect) local bus . PCI9054 is used as a bridge chip between the PCI local bus, FIFO data bus and CPLD control bus. It complies with the PCIv2.2 specification of 32-bit 33MHz bus master interface controller. The ADC uses AD9283, 8-bit resolution and a maximum conversion rate of 100M/s. Two FIFOs are used as data buffers and LatticeCPLDispMACHLC4128V is used for logic control between various chips. The software system uses Windriver to develop drivers and VC integrated development environment to write applications.

1.1 Hardware Design

Figure 2 shows the block diagram of the hardware part of this data acquisition system: In this hardware block diagram, PCI9054 connects two FIFOs to the PCI local bus of the PC.

Features of the PCI9054 interface chip: The 32-bit 33MHz bus master interface controller that complies with the PCIv2.2 specification can achieve PCI burst transfer speeds of up to 132 megabytes/second; it has two DMA engines, programmable target and initiator data transfer modes and PCI information transfer functions; 3.3V, 5V fault-tolerant PCI signals support universal PCI adapter design; flexible 3.3V, 5V fault-tolerant local bus operation, up to 50MHz; 32-bit multiplexed or non-multiplexed local bus supports 8-bit, 16-bit and 32-bit peripherals and storage devices; industrial temperature range operation, etc.

In this design, the slave target mode and DMA mode in PCI9054C mode are used. The sampling rate and sampling depth are set by sending various command control words to CPLD from the slave target mode. Through the DMA mode, the data collected and stored in FIFO is transferred to the computer's memory through the DMA channel 0 of PCI9054. In order to prevent the data collected by ADC from being overwritten, two FIFOs are used to store data alternately. The data storage and reading timing is shown in Figure 3.

The trigger pulse in the figure is sent by the Belson200AB ultrasound instrument. It is the trigger signal for a group of array elements of the instrument to transmit and receive ultrasound waves, with a period of 320μs. The 80-element R60 convex array probe of the Belson200AB ultrasound instrument is divided into 160 groups of array elements, that is, an original B-ultrasound image is composed of 160 lines of data. Data acquisition is to collect a certain amount of data for each line (the amount of data collected can be controlled by CPLD), start sampling data at the falling edge of the trigger pulse, and latch the number address of the line in the array element group (the address is generated by the Belson200AB ultrasound instrument and connected to the I/O port of the acquisition card CPLD through the cable). When the preset data volume is reached, the PC is notified to read the data and address from the FIFO into the PC memory. The logic of the two FIFOs working alternately is realized by CPLD. [page]

PCI9054 supports two types of DMA transfer: block transfer and scatter/gather transfer. Fast transfer is relatively simple, and Figure 4 is a schematic diagram of its transfer. Just write the corresponding values ​​to the various DMA control registers of PCI9054, such as the PCI address register stores the starting address of a continuous memory block on the PC side of this DMA, and the Local address register stores the starting address of the Local bus side (here is the address of the FIFO memory), etc.

Scatter/Gather transmission is relatively complex. In this transmission mode, the DMA controller loads the transmission parameters from the transmission list in the PCI or Local bus memory, where each node includes the PCI address, Local address, and the amount of data to be transmitted. At the same time, the address pointer of the next transmission node must also be added. When the DMA is started, it automatically passes the set parameters to the corresponding registers, so that multi-address and multi-data fast transmission can be achieved through a transmission list. The DMA controller determines whether a transmission has ended by checking the end flag of the list. These two methods can be selected by setting Bit9 of the DMA control register DMAMODE0 of the PCI9054.

The read and write timing control of the slave mode and DMA mode is realized through the logic control in the CPLD (the single-cycle read and write timing of the slave mode and the read and write timing of the DMA mode can be referred to the PCI9054 DataBook). In order to realize these two methods, we designed a simple state machine to realize it (as shown in Figure 5). The S1 state indicates the beginning of a transmission cycle; the S2 state indicates a single transmission cycle; the S3 state is a burst transmission cycle. When the PC writes a control command to the CPLD through PCI9054, the state machine should switch from S0→S1→S2→S0; and when the PC reads FIFO data through PCI9054 in DMA mode, the state machine should switch from S0→S1→S3→S0.

Figure 6 is a simulation of the state machine controlling the FIFO read timing , and the result meets the requirements of our state machine design. In this figure, LCLK is the local clock of PCI9054, LHOLD is the request signal of PCI9054 for applying for the local bus, and LHOLDA is the response signal for the local bus application; ADS_(ADS#) is valid to indicate the start of the read and write operation cycle; BLAST_(BLAST#) is valid to indicate the last cycle of the operation; LWR_(LWR#) low level indicates the read cycle, and high level indicates the write cycle; ROE_FIFO output enable signal; REN_FIFO read enable signal; READY_(READY#) is valid to indicate that the local end data is ready.

Double-layer PCB is used in PCB design. PCI signal lines are wired according to the electrical specifications of PCI local bus. The length of signal lines shall not exceed 1.5 inches. 33M clock routing shall be controlled within 2.5±0.1 inches. The serpentine routing can be used to achieve this routing length. In order to reduce the interference of digital signals on analog signals, the power supply and ground of analog signal part and digital signal part are isolated respectively. The power supply of PCI bus is supplied to analog power through DC-DC conversion; and the connection point of analog ground to digital ground is isolated with high-frequency magnetic beads; at the same time, in order to reduce the attenuation and interference of RF signals during transmission, the access of RF signals is connected by coaxial cable.

1.2 Software Design

The software writing calls the API function of Windirver as the driver function of various read, write and control operations of the data acquisition card. Windriver driver writing is simple and

And it provides the sample program of PLX PCI interface chip, which greatly improves the development efficiency. The whole software system is developed with VC6.0, the main program calls and coordinates the operation of each WindriverAPI function, and completes the data storage, image display, etc.

The application interface is based on the Dialog class, and the application mainly consists of four classes as shown in Table 1. The base class of CUSoundSconnerDlg is the CDialog class, which is used to display the program interface and accept various user inputs.

The PCI9054CARD general class encapsulates the API functions of Windriver and is used to manage various operations of the data acquisition card, including initialization of the acquisition card, DMA data transmission, and writing of various control commands. The CDisplayImage thread class is used to display the read data on the PC screen in the format of a BMP image, and also completes the saving of the BMP image. The CGetDatafromDevice thread class reads the data in the FIFO into the PC memory in DMA mode and saves the data on the PC hard disk. This thread class always queries the FIFO data ready full signal during its lifetime, and starts DMA to read data when the signal is valid.

2 Experimental Results

Figure 7 shows a set of echo signals received by the data acquisition system. It can be seen from the figure that there are three strong echo signals. The first one (from left to right) is the echo of the probe, and the second and third ones are the reflected waves from the upper and lower surfaces of the object being measured. The high-frequency noise is about 1%.

FIG8 is a frame of image composed of echo signals received by 160 array elements according to the number, that is, the data shown in FIG7 is directly represented by a 256-color grayscale image. In the figure, it can be observed that there are three places with stripes of different grayscales. The first place (from left to right) is formed by the echo formed when the ultrasound probe exits, and the second and third places are formed by the echoes of the upper and lower surfaces of the object being measured. This is consistent with the echo signal received by a single group of array elements shown in FIG7.

3 Conclusion

This data acquisition system can quantize the radio frequency signal of Belson 200AB ultrasonic diagnostic instrument into digital signal, and transmit the data to PC for display and storage through DMA. The high-frequency noise is controlled at about 1%, which provides good experimental data for estimating the system function and digital signal processing algorithm of the system. By writing control words to the CPLD device, the system can achieve dynamic control of sampling rates of 80M, 40M, and 20M and sampling depths of 2K and 4K. At the same time, this system can also be used for high-speed data acquisition of other radio frequency signals.