Debugging of radar signal processing system based on ADSP21062

ADSP2106x SHARC is a high-speed 32-bit digital signal processor suitable for voice, communication and image processing. The chip is a complete single-chip system developed based on the ADSP21000 series DSP chip, with an additional dual-port on-chip SRAM and integrated I/O devices. With its on-chip instruction cache, the processor can execute each instruction within one clock cycle. ADSP2106x SHARC embodies a new integration standard for digital signal processors. It combines a high-speed floating-point DSP main processor with integrated on-chip components, including a host interface, DMA controller, serial port and connection port. Due to its fast processing speed and convenient connection and communication of DSP multi-processing systems, it has been developed and applied in more fields. However, how to debug the processing system based on ADSP2106x is a key issue that people must solve when applying this chip. This paper proposes a simple and easy test method, which has been successfully debugged in the radar signal processing system based on ADSP21062, verifying the feasibility of this method.

1 Introduction to Radar Signal Processing System Design

We designed a radar signal processing system using the ADSP21062 processor. This system can work independently or communicate with other DSPs through the Link port. ADSP21062 uses the JTAG interface to connect to the EZ-ICE simulator to simulate and test the system. The circuit structure of the system is shown in Figure 1.

The EZ-ICE emulator uses the IEEE1149.1 JTAG test standard to monitor and control the operation of the target board processor. The test head of the EZ-ICE emulator is connected to the CLKIN (optional), TMS, TCK, TRST, TDI, TDO, and GND signals of the target board processor through a 14-pin connector. A 14-pin interface is designed on the circuit board, and its signal interface is shown in Figure 2.

2 Circuit Testing

The circuit test mainly uses the EZ-ICE simulator. The simulator is inserted into the ISA slot of the PC and connected to the ADSP21062 processing system through the JTAG port. The DSP system operation can be monitored in real time on the PC monitor using the Emulator control interface. ADSP2106x provides two sets of software, Simulator and Emulator. Their interfaces are exactly the same, except that one does not require hardware and the other does. The test program can be assembled by the Assembler first, and then simulated by the Simulator. Finally, under the control of the Emulator interface, the executable file (.EXE file) and the assembled structure file (.ACH file) generated by the assembly can be loaded to realize the testing and simulation of the hardware.

2.1 Basic Operations of Hardware Testing

When testing the hardware, first perform simple operations on the internal control, status register and memory of the memory to confirm that the communication between the EZ-ICE emulator and the processor is normal.

There are generally two types of operations on registers: bit operations and word operations2~3.

(1) Bit operation: The bit operation of register is mainly used for BIT SET and BIT CLR.

For example: BIT SET MODE2 0x00000001

BIT CLR MODE2 0x00000001.

The above operations set or clear the first bit of MODE2 without affecting other bits.

(2) Word operation: The word operation of the register uses the DM() addressing instruction.

For example: R0=0x00000001;

DM(SYSCON)=R0.

The above operation sets the first bit of SYSCON and clears the other bits.

The memory operation is performed using the DM() instruction. Direct addressing, indirect addressing and indexed addressing can be implemented by adding immediate data, register Rx (the content is the addressing value), base address (Ix) and index address (Mx) to the instruction.

For example: R0=0x23;

DM(0x00030000 =R0.

The above operation will put 0x23 into the address 0x00030000. [page]

2.2 System operation test

Design an operation for the four indicator lights of the FLAG bit to make them flash alternately to check whether the ADSP21062 processor can run normally. The program uses the interrupt method and generates two interrupts TMZHI and TMZLI when the timer overflows. One interrupt service program sets the indicator lights of FLAG0 and 1 to be on and the indicator lights of FLAG2 and 3 to be off; the other interrupt service program sets the opposite. The two service programs are executed alternately, and the alternating interval is determined by the initial value of the timer. The program flow chart is shown in Figure 3.

Since the processor MODE2 register is cleared when the system is reset, the FLAG pin is used as an input and the processor cannot change its state. Therefore, the main program needs to initialize it and make the FLAG pin an output before changing the state of FLAG in the ASTAT register. Similarly, the timer must also be set.

(1) Timer setting:

BIT SET MODE1 0x1000; (Open global interrupt)

BIT SET MODE2 0x20; (Open timer)

BIT SET IMASK 0x10; (Open TMZHI interrupt)

(2) Setting of FLAG bit:

BIT SET MODE2 0x78000; (set to output)

BIT CLR ASTAT 0x180000; (FLAG0 1 is on)

BIT SET ASTAT 0x600000; (FLAG2 3 off)

This program can be tested by JTAG simulation. Use a universal programmer to write this program into EPROM, and then let the system work alone to verify whether the system can boot and work normally. After power-on, the four indicator lights flash alternately, and it is verified that the system has successfully completed the boot and works normally.

2.3 Link port test

Use a transmission line to connect the two Link ports of the processor, then let one Link port send data and the other receive data, test it using the Emulator JTAG single-step execution method to observe the sending and receiving process.

(1) Setting the Link port transmission rate:

R0=0x00006000;

DM LCOM =R0; 2x rate)

(2)LBUF setting:

R0=0x0003fe8f;

DM LAR = R0; LBUF1 for Link port 1, LBUF2

For Link port 2)

(3) Open Link port:

R0=0x00000190;

DM LCTL = R0; Link port 1 sends, Link port 2 receives)

(4)Transmission operation:

R0=0x12345678;

DM LBUF1 = R0; Link port 1 sends 0x12345678)

R1=DM LBUF2; Get the data received from Link port 2)

After testing, the Link port works normally. Through the Link port control window of the Emulator, we can see that: when the Link port is set up, when the DM(LBUF1)=R0 instruction is executed, we can see that the status of the Link port 2 buffer (through the LxSTAT register) has data; when the R1=DM(LBUF2) instruction is executed, the status of the Link port 2 buffer is empty, and the value of register R1 is the content of the Link port 1 buffer (LBUF1). This proves that the data can be successfully transmitted to Link port 2 through Link port 1, and communication between processors can be completed through the Link port.

2.4 DSP algorithm execution time

Put a DSP algorithm written in assembly language into the system through EZ-ICE emulator for execution. The clock (instruction) counting function provided by Emulator can tell the actual execution time of the algorithm in the processor. There is a clock count (Cycle Count) in the counting window of Emulator, which records the number of clock cycles used from the start to the stop of the program. The total execution time can be obtained by multiplying the number of clocks (Cycle Count) by the clock cycle.

Aiming at the development and research of ADSP2106x processing system, this paper proposes a simple and easy test method which can not only judge whether DSP can work normally, but also test the validity of information transmitted through Link port when multiple processors are interconnected. The proposed test method has been verified in the debugging of radar signal processing system based on ADSP21062 developed by us.