Design of High-precision Arbitrary Waveform Generator Based on DDS

With the rapid development of digital signal processing technology, the emergence and widespread application of high-precision and large dynamic range D/A converters, the synthesis technology based on sampling technology and computing technology, which generates relatively fixed and adjustable frequency and phase through digital methods, that is, direct digital frequency synthesis (DDS) technology is becoming increasingly mature. It adopts a fully digital structure and has the advantages of high frequency resolution, relatively wide bandwidth, fast frequency conversion speed, low phase noise, high signal purity, etc. Therefore, this system uses DDS technology to complete the design of arbitrary waveform generator.

1 DDS Working Principle

Direct digital frequency synthesis (DDS) technology is a fully digital waveform generation method based on the sampling theorem. The DDS frequency synthesizer is mainly composed of a phase accumulator, a waveform data memory, a D/A converter and a low-pass filter. Its principle block diagram is shown in Figure 1. In one system clock cycle, the phase accumulator adds the previous accumulated value to the frequency control word to obtain a new accumulated value. The new accumulated value is used as the address to read the amplitude value of the signal from the waveform data memory, and send it to the D/A converter to convert the digital signal into an analog signal. Finally, the required waveform is generated through a low-pass filter. The waveform data memory stores the amplitude value of a single cycle of the periodic signal. Every time the phase accumulator overflows, the signal amplitude value of one cycle can be read from the waveform data memory. Therefore, if the frequency control word is assumed to be K and the phase accumulator is N bits, a one-cycle output signal can be generated after a system clock cycle. If the system clock frequency is set to fsclk, the output signal frequency is fsclk.

2 System overall block diagram

The overall block diagram of the system is shown in Figure 2. Among them, the upper computer software is written by LabWindows software, which is used to control the generation of signals. The lower computer uses FPGA as the core control device, which is mainly used to receive the control commands and signal parameters sent by the upper computer, and control the lower computer system to generate corresponding waveforms. The lower computer system is mainly divided into FPGA control unit, waveform storage unit, and waveform generation unit. The waveform storage unit mainly includes FLASH and SRAM. FLASH is used to store various waveform data. When the waveform is generated, FPGA first reads the waveform data to be generated from FLASH into SRAM, and then uses the accumulated value of the phase accumulator to read the waveform data from SRAM. The waveform generation unit mainly completes the generation of waveform data. First, the waveform amplitude data read from SRAM is sent to the D/A converter to generate the step sequence wave of the signal, and then the output signal is generated through the low-pass filter and power amplifier circuit.

3 System Hardware Design

3.1 FLASH connection circuit diagram

FLASH uses S29AL032D from Spansion Semiconductor, USA, with a capacity of 32 MB. It is used to store the amplitude information of various waveforms. Its storage form is shown in Figure 4.

As shown in Figure 4, the address range 0x000000 to 0x01FFFF stores the sine wave amplitude value, the address range 0x020000 to 0x03FFFF stores the triangle wave data, the address range 0x040000 to 0x05FFFF stores the sawtooth wave data, the address range 0x060000 to 0x07FFFF stores the white noise data, and the address range 0x080000 to 0x0FFFFF is 4 user-defined areas, which store 4 types of periodic waveform data that the user needs to generate.

3.2 RAM connection circuit diagram

The RAM adopts IS61LV25616AL-10T from the American semiconductor company, with a capacity of 256×103×16 bits. It is mainly used to store the control commands sent by the host computer and the amplitude value of the signal when the waveform is generated. Its storage form is shown in Figure 6.

The address range of Ox00000 to 0x1FFFF stores the control commands and data parameters sent by the upper computer to the lower computer, and the address range of Ox20000 to Ox2FFFF stores the waveform amplitude value of the signal to be generated by the system.

3.3 Signal generation circuit connection diagram

Figure 7 is a circuit connection diagram for generating arbitrary signals, and the generated signal frequency range is 50 Hz to 200 kHz. Among them, AD768 is a 16-bit high-precision D/A converter with a maximum update rate of 40Msps, which meets the design requirements.

4 System Software Design

4.1 Host computer software design

The upper computer part is written by Labwindows software, which is mainly responsible for the control of the lower computer system, including the setting of signal frequency, amplitude, phase (duty cycle), signal waveform selection, input of user-defined waveform data, etc. Its control panel is shown in Figure 8.

4.2 FPGA Software Design

FPGA is the core control unit of the system, responsible for communicating with the host computer software and controlling the slave computer system to generate arbitrary waveforms.

4.2.1 Design of communication module with host computer

The communication between the upper computer and the lower computer is realized through RS232. FPGA is mainly used to receive the data sent by RS232 and store it in the external RAM. The communication module is shown in Figure 9.

The RS232_Controller module is used to receive data sent by the host computer. The RS232 rate is 115.200 kB/s, with 8 data bits, 1 stop bit, and no parity bit. The data_buffer caches the data received by the RS232_Controller and combines them into 16-bit data in the order of reception and then sends them to RamWrite. RamWrite then stores these 16-bit data in the external RAM starting from address 0x00000.

4.2.2 Receive data processing module

This module is mainly used to analyze and process the received host computer data, and extract the signal data information, various parameters and control commands from it, as shown in Figure 10.

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When RS232 completes sending data, the receiving data processing module immediately starts reading the data in the RAM from address 0x00000. When the first data and the second data are 16\'hAAF0 and 16\'hBB55 respectively, the high 8 bits of the third data are the command control word, otherwise the receiving data processing module stops reading the data in the RAM. The meaning of each bit of the 8-bit command control word is as follows

A represents the command control word, and A[n] represents the nth bit of the command control word, then:

When A[15] is 1, it indicates storing user-defined waveform data, and when it is 0, it indicates generating arbitrary waveforms. When storing waveforms, A[14:8] is 0, which indicates storing waveform data in user-defined area 1; 1 indicates storing in area 2; 3 indicates storing in area 3; and 4 indicates storing in area 4. The fourth data read is user-defined waveform data, totaling 65,536, and ends with 16\'h65 80 and 16\'h0856. Its storage format is shown in Figure 12.

When generating arbitrary waveforms, A[14:11] is 0 for generating sine waves; 2 for generating square waves; 3 for generating triangle waves; 4 for generating sawtooth waves; 5 for generating Gaussian white noise; 6 for generating user-defined waveforms in zone 1; 7 for generating user-defined waveforms in zone 2; 8 for generating user-defined waveforms in zone 3; and 9 for generating user-defined waveforms in zone 4. The 4 16-bit data read from RAM represent the frequency (32 bits), amplitude, phase (duty cycle for square waves) and control words of the waveform to be generated. The data storage format is shown in Figure 13.

4.3 FLASH data access module design

This module is used to store and read waveform data. In the signal generation mode, it determines the waveform to be generated based on the data input by Sig_Type[3:0], and then reads the data information of the corresponding waveform from FLASH and stores it in RAM. When Sig_Type[3:0] is 1, it means generating a sine wave; when it is 2, it means generating a square wave; when it is 3, it means generating a triangle wave; when it is 4, it means generating a sawtooth wave; when it is 5, it means generating Gaussian white noise; when it is 6, it means generating a user-defined 1-zone waveform; when it is 7, it means generating a user-defined 2-zone waveform; when it is 8, it means generating a user-defined 3-zone waveform; when it is 9, it means generating a user-defined 4-zone waveform.

4.4 Waveform generation control module

The module uses DDS technology to control AD768 to generate arbitrary waveform signals, as shown in Figure 15.

fre_ctrl, amp_ctrl, phase_ctrl are the frequency control word, amplitude control word and phase control word of the waveform respectively. clk is the control clock of this module, and its 6-frequency clock is the 32-bit phase accumulator clock. In a phase accumulator clock cycle, the module uses the sum of the high 16-bit accumulated value of the accumulator, the phase control word and 18\'h20000 as the RAM address to read the data of the waveform signal from the RAM. Let this data be data, then the data output by the D/A is, and then this data is sent to AD768 at the rising edge of clk_da, and it is circulated in sequence. The output of AD768 will generate a step-shaped signal waveform, and then pass through the low-pass filter and power amplifier to obtain the waveform to be generated. Figure 16 shows the 5V, 200kHz sine signal generated by the system.

5 Conclusion

The design of arbitrary waveform generator, the design of system hardware and software programming have been completed. After testing, the system can generate common signals such as sine wave, square wave, sawtooth wave, triangle wave, Gaussian white noise in the frequency band of 50Hz~200kHz. The signal generator has the advantages of high frequency resolution, fast frequency conversion speed, high signal purity, and multiple types of generated signals. It can be widely used in communication systems, automatic control systems, instruments and meters, electronic countermeasures, remote control and telemetry, etc.