1. Introduction to ADF4360-2 chip
ADF4360-2 is a high-performance phase-locked frequency synthesis chip produced by ADI of the United States. It integrates an integer N synthesizer and a voltage-controlled oscillator and can be used in wireless handheld communication equipment, detection equipment, wireless LAN and cable TV equipment. The main features of this device are as follows:
◆The output frequency range is 1850~2170MHz, and supports binary output. When binary output is selected, the output can be 925~1085MHz;
◆The operating voltage is 3~3.6V;
◆Programmable dual-mode prescaler 8/9, 16/17, 32/33;
◆Programmable output signal power control;
◆Capable of analog and digital lock detection;
◆Support software and hardware power-off functions.
The functional block diagram of ADF4360-2 is shown in Figure 1. It mainly consists of a 14-bit programmable reference R counter, a 24-bit data register, a 24-bit function latch, a voltage-controlled oscillator, a phase comparator, a lock detector, a multiplexer, and a charge pump.
2. Frequency synthesis system circuit design
Through the external frequency source signal and the microcontroller control signal, the 14-bit programmable reference R divider divides the external frequency source signal to obtain the reference frequency and send it to the phase detector. The control signal consists of the clock signal CLK, the data signal DATA and the enable signal LE. Under the control of CLK, the 24-bit data signal is serially input and temporarily stored in the 24-bit data register. After receiving the enable signal LE, the previously input 24-bit data reaches the corresponding latch according to the address bit. The main frequency division ratio N of ADF4360-2 is realized by a dual-mode pre-divider (P/P+1), a programmable 5-bit A counter and a 13-bit B divider. The algorithm is N=B×P+A, and the output frequency is fVCO=(B×P+A)×fREFIN/R. The control of the phase-locked loop is realized by setting the control words of the three control word registers A, B, and R. The chip only needs to add a loop filter to the periphery and select appropriate parameters according to the output frequency to output a more stable frequency. The circuit system structure block diagram is shown in Figure 2.
The loop filter network has a low-pass characteristic, which mainly suppresses the carrier frequency component and high-frequency noise in the phase detector output voltage and reduces the parasitic output caused by the impure VCO control voltage. The loop filter network shown in Figure 2 can be simulated and designed using the dedicated design and simulation tool software ADIsimPLL provided by ADI.
3. Chip configuration program design
In this circuit design, the PFD input frequency of ADF4360-2 is 1MHz, so the reference clock frequency division R=40. From the formula fVCO=(B×P+A)×fREFIN/R, it can be calculated that N is 11250, the dual-mode pre-frequency is set to P/(P+1)=32/33, counter A is set to 8, and counter B is set to 32. According to the ADF4360-2 chip data, the three control registers are initialized to R register 00000A1H, C register 8FF12CH, and N register 803E42H. The configuration values are listed in Table 1.
The MCU configures the internal registers of ADF4360-2 by providing the clock signal CLK, data signal DATA and enable signal LE, so that the VCO outputs the signal of the required frequency. At the same time, it is responsible for detecting the lock flag of ADF4360-2. If the detection is locked, the configuration data work is completed. The MCU program flow is shown in Figure 3.
Conclusion
This paper introduces the design of 1GHz signal output method using phase-locked frequency synthesis chip ADF4360-2, and gives the circuit system structure block diagram and single-chip program flow. Since ADF4360-2 has an internal integrated VCO and the control word is written externally through the single-chip I/O port, the system has the characteristics of simple peripheral circuits, convenient debugging, low power consumption and cost, and can be widely used in various circuit systems.
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