Design of real-time data acquisition system based on ADmC812 and DSP

Introduction

ADmC812 is a new micro converter of ADI with 8051 (8052) core as the control core. Because ADmC812 integrates a large number of peripherals. It is a fully programmable, self-calibrated, high-precision data acquisition system that can replace the traditional MCU+A/D+ROM+RAM high-cost, large-volume products, especially its high-precision and high-speed A/D module, which is particularly suitable for intelligent sensing, instantaneous acquisition, data acquisition and various communication systems. However, for occasions where a large amount of data needs to be collected, the calculation is complex, and the real-time requirements are high, it is often unable to meet the requirements due to the limitations of structure and speed. In view of this situation, this paper proposes a data acquisition system based on ADmC812 and DSP. In this system, ADmC812 is the host to complete the functions of ADC, DAC, display, keyboard, etc., while DSP is the slave to focus on complex data calculations. The two realize data exchange and communication through a common SRAM.

Introduction to ADmC812 and TMS320F206

ADmC812 microconversion chip

ADmC812 is an 8051/8052 microcontroller with 16-bit counter/timing and 32 programmable I/O interfaces. It has an 8-channel, 5ms conversion time, precision self-correction, 12-bit successive approximation ADC, two 12-bit DACs, 10.5KB flash EEPROM, and 256 bytes of SRAM. It also includes some important functional modules, such as watchdog timer and power monitor, DMA mode between ADC and data memory, storage protection function, a universal asynchronous serial receiver and transmitter (UART), SPI and I2C bus interface.

The rich peripherals in ADmC812 make it possible to form a complete data acquisition system without external bus expansion, which has a high cost-effectiveness. More noteworthy is that ADmC812 integrates 8-channel 12-bit high-precision, self-calibrated 4ppm/℃ ADC circuits. Moreover, when the working conditions (such as clock frequency, analog input range, reference voltage or power supply voltage) change, in order to obtain high-precision ADC results, the 4 special function registers for correction in ADmC812 can be set by software to achieve the purpose of further calibrating the ADC. By setting the three special function registers ADCON1~3, ADmC812 can make the ADC work in 3 different modes, realizing single conversion, continuous conversion and DMA mode A/D conversion, which can be selected according to specific needs. In DMA mode, the ADC is allowed to continuously sample after each setting of registers ADCCON1~3, and the results are written to the external RAM. This automatic capture function greatly facilitates the data exchange between the master and slave processors.

Digital Signal Processor TMS320F206

TMS320F206 (hereinafter referred to as F206) is one of the TMS320C2000 series DSPs produced by TI. It is a low-cost, high-performance 16-bit fixed-point DSP launched after C2X and C5X. Because it adopts an improved Harvard structure, has a separate program bus and data bus, and adopts a four-stage pipeline operation, its operating speed can reach 40MIPS, and it has the characteristics of high-speed operation. At the same time, it provides a rich instruction set and an enhanced modular structure design, which improves its versatility and continuously expands its application field. It has now become an ideal substitute for high-end single-chip microcomputers. F206 has a 32K flash memory on the chip. Users can simulate and debug the program through the JTAG interface that comes with F206 and complies with IEEE standard 1149.1, and burn the program code into the chip, which greatly facilitates the user's system design and program debugging.

TMS320F206 provides direct memory access (DMA) function, which allows direct memory access to external programs, data and I/O space by using HOLD operation. The process is controlled by two signals, A15, A20 and A30. External devices can drive the pin to a low level to request control of the external bus. If the interrupt line is allowed, an interrupt will be triggered. When F206 responds to the interrupt, the software logic can make the processor send a response signal to indicate that it will give up control of the external bus. According to A15, A20, A30, A40, A50, A60, A70, A80, A90, A90, A10, A110, A120, A130, A140, A150, A160, A170, A180, A190, A200, A200, A300, A400, A500, A600, A700, A800, A900, A100, A110, A120, A130, A140, A150, A160, A170, A180, A19 ...30, A140, A150, A1

System hardware design

The hardware structure of the system is shown in Figure 1. The memory 62256 is used as the global data memory of DSP and the external memory of ADmC812. The two controllers are connected to the data memory 62256 through the bus to realize memory sharing. In order to ensure that the two controllers can work independently, four 74HC245s are inserted between ADmC812 and 62256 for bus isolation. In this way, under the control of ADmC812, only one controller accesses 62256 at any time. In the figure, 62256 is used as the external memory of ADmC812, A15 is the chip select signal, and the address range is 8000H~FFFFH; as the global data memory of F206, it is used as the chip select line and uses the high-end 32K word address range (8000H~FFFFH). The two chip select signals are connected to the chip select line CS2 of 62256 through a NAND gate to realize the isolation of the chip select signal.

ADmC812 is connected to the XF pin of DSP through P1.0 and P3.2 (INT0), and P1.0 requests bus control from DSP. After DSP responds to the request of ADmC812, the CPU of DSP is suspended and the external bus is released. ADmC812 opens the bus driver through A15, selects 62256 after the NAND gate, obtains the control right of 62256, and realizes the read and write operation of 62256. F206 can also request an interrupt from ADmC812. After responding to the interrupt INT0, ADmC812 processes related transactions. On the other hand, ADmC812 can confirm whether F206 is suspended by reading the level of the pin; and by controlling the pin, the branch transfer of F206 program is realized, increasing the flexibility of the system.

The whole system is divided into transactional module and data processing module. ADmC812 controls the transactional module to collect data, display LED, input and output of switch quantity, output of analog quantity and serial communication. F206 controls the data processing module, mainly processes data and completes complex algorithms. In addition, some important export control functions can also be directly processed according to the data processing results to make up for the shortcomings of ADmC812 I/O port and speed up the response speed of the system. Two relatively independent functional modules exchange data through 62256.

System software design

Since the two modules of the system are relatively independent in function, the corresponding software also includes two main modules. After the program is loaded, ADmC812 enters the normal operation of the program. After the system is initialized, it first requests DMA operation to F206 through P1.0, and after receiving a response, ADmC812 obtains the control of 62256. At this time, by configuring the three special function registers ADCCON1~3, ADmC812 can work in different modes. In DMA mode, ADC can convert continuously and capture the sampled values ​​to the external RAM space without any intervention from the microprocessor. The interrupt bit ADCCON2.7 indicates the end of DMA conversion. After the A/D conversion is completed and the sampling points reach the predetermined number, ADmC812 gives up the control of 62256 through the ADC interrupt and notifies the DSP to process the data. Then ADmC812 enters transactional work such as display, key function, I/O operation, and serial communication.

After receiving the DMA request from ADmC812, F206 enters the waiting state and gives up the control of the external bus. 62256 obtains the sampled data through ADmC812. When the sampling is completed, DSP returns from the waiting state to the normal operation state and obtains the control of the bus, performs data processing, and puts the operation result back to 62256. The DMA operation process of F206 is: a valid falling edge is obtained on the F206 pin /. When the CPU transfers to the 0002H address unit, the CPU extracts the interrupt vector from the 0002H address unit and enters the interrupt service program. After successfully testing MODE=0, the interrupt service program executes an IDLE instruction to put F206 into the waiting state. When a rising edge on the / pin is detected, the CPU exits the IDLE state, returns the external bus to its normal state, and executes the data processing program.

The software is designed in C language, and the program design and debugging are carried out on two development systems respectively. Using the software development tools provided by ADI, the design of ADmC812 application program can be completed quickly and efficiently, and online debugging and code download can be performed through the universal serial port of ADmC812. F206 uses the TDS-510 development tool provided by Wenting Company for software design. Finally, ADmC812 and F206 are debugged online to complete the development of the entire software.

Conclusion

The above design is suitable for applications with large amounts of collected data, complex algorithms, and certain real-time requirements. Since the dual-CPU system does not require additional dual-port RAM, FIFO, and complex control circuits, it reduces costs, simplifies circuits, and expands the application range of ADmC812.