Design of acoustic detection system based on TMS320VC33-150-EEWORLD

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Introduction

Passive sound source detection and positioning technology is a technology that uses acoustic microphone arrays and electronic devices to receive the radiation noise of moving targets to determine the location of the target.

This article is based on the principles of acoustic detection technology and mature microelectronics technology, using TI's 32-bit floating point DSP chip TMS320VC33-150 to implement the detection and positioning algorithm of sound source targets, supplemented by ADC, CPLD, microcontroller and other devices. Realize the collection of sound source signals, system logic control and communication functions. For the logic control function of the digital circuit, this article uses Altera's CPLD chip EPM7128AETC100-10 to implement it. The chip has low power consumption, rich resources, and fixed internal delay, which is helpful for the design of sequential logic circuits. This system is mainly divided into two parts: hardware implementation of the digital circuit of the acoustic detection system and DSP software design. The system has now been debugged, runs stably, and has good detection results.
　　
System Function

The sound detection system obtains the radiation noise information of the sound source target through the microphone array. After processing the front-end analog signal, the DSP performs high-speed sound detection positioning algorithm processing in the digital circuit, and converts the obtained sound source orientation, speed and other information , sent to the computer terminal for convergence display.

Hardware design of acoustic detection system

In the acoustic detection system, digital circuit is the most critical part. This article uses DSP, CPLD and microcontroller as core devices to complete the hardware design of the digital circuit of the acoustic detection system. The digital circuit block diagram is shown in Figure 1.

　　　　　　　　　　　　　Figure 1 Digital circuit block diagram of the acoustic detection system.

After the front-end processed analog signal is sampled and converted by the AD7865, an interrupt is given to the DSP. With the cooperation of the CPLD, the DSP reads the data of each channel and stores it in the off-chip SRAM data area. At the same time DSP performs digital filtering and spectrum analysis on the data to complete the positioning function of the sound source target.

The dual-port RAM realizes the exchange of target information between DSP and C8051F020, and finally completes the RS-422 communication with the terminal through MAX3485. In addition, the DSP implements gain control of the front-end analog circuit based on the processed results.

ADC design The

passive sound detection system has high requirements for the phase consistency of the sound. Therefore, the 14-bit parallel output ADC AD7865 with simultaneous sampling and holding function is used in the design. In this design, the 6-channel sound source target signals after amplification and filtering are implemented through two AD7865s for A/D conversion. This article uses the output signal of the DSP timer as the start sampling signal of the ADC. After the sampling conversion is completed, an interrupt is given to the DSP through the BUSY signal of the ADC, and then the DSP enters the interrupt handler to read the A/D data, and the read and write signals and the ADC The chip select signal is completed by the CPLD logically combining the read and write signals and address signals of the DSP.

DSP and peripheral circuit design

The main function of DSP is to complete the automatic gain control of the front-end analog signal according to the amplitude of the collected digital signal. The gain control levels include 16, 64, 256, 1024, 4096, 16384, and 65536, a total of 7 levels. ; Perform operations such as digital filtering, fast FFT transformation, and orthogonal transformation on the collected data to complete operations such as target positioning and identification; complete communication with the microcontroller through dual-port RAM, and timed start of the ADC.

DSP peripheral circuit includes program boot area Flash, program running area SRAM, data exchange area dual-port RAM and gain control. Flash uses AMD29LV040B with a capacity of 1M*8b to form the code storage space; SRAM uses SRAM memory CY7C1049-CV33 with a capacity of 512K*8b. Four slices are used in the circuit for bit expansion, thus forming a 512K*32-bit program running space; The dual-port RAM is 2K*8-bit IDT71V321; and the gain control is implemented using an 8-bit CMOS latch.

TMS320VC33-150 has four external interrupts, all of which can be used as BootLoader interrupts. Therefore, BootLoader prefers high-priority interrupts, otherwise it may not be able to load the program successfully during offline power-on. Because after power-on reset, the DSP executes the resident program and searches for the BootLoader storage area according to the interrupt level. If the interrupt higher than the BootLoader interrupt is not invalidated, the DSP will search for the BootLoader storage area according to the high priority, thus causing the program to Loading failed.

In addition, during the design process, some important signals such as #RDY, #HOLD, EDGEMODE, MCBL/#MP, #SHZ, etc. must be pulled up or pulled down according to the specific design and refer to the data manual. During the debugging process of this design, the #HOLD signal was not processed, so the program could not be downloaded online. This was finally solved by pulling it high.

Table 1 Correspondence table between interrupt number and program loading address

Figure 2 DSP software program design flow chart

Logic control

This design uses Altera's EPM7128AETC100-10 to realize the timing management and logic control functions of the entire circuit system, which mainly includes ADC control function module, memory read and write timing control module, communication interface timing control module and gain control. And generate chip select signals and read and write timings based on DSP external memory address space decoding. In this design, QuartusⅡ is used to complete logic control simulation.

MCU circuit

C8051F020 MCU is a fully integrated mixed-signal system-level MCU. In addition to the digital peripheral components of the standard 8051 MCU, the chip also integrates analog components and other digital peripherals and functional components commonly used in data acquisition and control systems.

In this design, the serial port of C8051F020 is used to realize RS-422 asynchronous serial communication with the computer terminal, with a baud rate of 19.2Kbps; the dual-port RAM is used to complete the real-time exchange of sound source target data between the DSP and the microcontroller.

When designing a microcontroller circuit, in order to ensure the reliability of the power-on reset circuit, you can use basic RC circuits and specialized monitoring integrated circuits such as MAX708T. At the same time, you should make full use of the MODEN VDD monitor function.

Auxiliary circuit

The auxiliary circuit includes crystal oscillator, watchdog, voltage reference circuit and DC/DC power module. The DSP clock uses a 15MHz crystal oscillator, which reaches the fastest operating speed of TMS320VC33-150 after being multiplied by 5 times inside the DSP. At the same time, a 20MHz crystal oscillator is used as the clock source of the microcontroller. In this design, the DSP is shut down by using the MAX706 watchdog chip. The voltage reference circuit uses TPS767D318 to provide +3.3V and +1.8V power for the entire system; the DC/DC power module completes efficient conversion of external +12V~+5V.

DSP software design

DSP software process

The entire software is based on interrupt mode. DSP software design includes ADC conversion startup, data acquisition, interrupt service routine, digital filtering of sound source signals, fast FFT and orthogonal transformation, as well as the MUSIC algorithm to obtain high-resolution spatial sound intensity distribution through spectrum analysis. The DSP software flow of the acoustic detection system is shown in Figure 2. ??

The workflow of the DSP software is: after the system is powered on and reset, load the external Flash program file to the external SRAM program area, and then run the DSP after initializing each part. The program always queries the ADC interrupt signal, and enters the interrupt service program after obtaining the ADC interrupt. The collected data is stored in the external SRAM data area, and then calls the detection and positioning program to obtain the orientation and other parameters of the sound target, and writes them to the external dual-port RAM. , for the microcontroller to read and then send to the computer terminal for fusion and rendezvous.

The DSP program BootLoader

TMS320VC33-150 has two working modes, and the selection of the working mode is determined by the MCBL/MP pin. In this design, by pulling up the MCBL/MP pin to a high level, the DSP works in microcomputer/boot load mode or external memory loading mode. After the Reset signal changes from low level to high level, TMS320VC32-150 first checks the external interrupt input line level to decide where to start the boot program. The relationship between the interrupt number and the corresponding start boot address is shown in Table 1 . The BOOT2 method is used in this design, that is, after the DSP reset signal changes from low to high, the DSP starts loading the program from the external storage address 400000H.

It should be noted that when using the external memory loading method, the loader must contain the data bus width of the external memory (8 bits, 16 bits or 32 bits), the length of the program code, the entry address of the program execution and the number of wait states of the memory.

In the process of loading the successfully debugged program into Flash, the method adopted in this article is to write a *.cmd conversion file, and then use HEX30.EXE to convert the *.out file into a *.hex file. And burn the generated *.hex file into Flash. Of course, online programming can also be used.

Conclusion

The digital circuit design of the acoustic detection system based on TMS320VC33-150 makes full use of the powerful floating point computing power of TMS320VC33-150, and successfully completes the algorithm processing of sound source target detection and positioning. At the same time, it also made full use of the logic control function of CPLD and the rich peripheral resources of MCU, and designed the DSP algorithm and interrupt service program flow. The system has been debugged and has undergone sufficient field testing. The results show that the system works stably and all indicators basically meet the requirements.

Keywords：CPLD Reference address：Design of acoustic detection system based on TMS320VC33-150

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