Design of driving fatigue detection system based on BF533

1 Introduction
Fatigue driving is one of the main causes of traffic accidents. According to statistics, traffic accidents caused by driving fatigue are the highest in both absolute numbers and proportions. How to effectively detect the fatigue state of the driver and give a warning or remind him to stop and rest when he is sleepy has become a research hotspot. The application of driver fatigue detection system to actively prevent traffic accidents can reduce the occurrence of traffic accidents to a certain extent, reduce the harm caused by traffic accidents, and make drivers' driving and public travel safer. At present, the methods of driver fatigue detection at home and abroad can be summarized into three types: ① Monitoring the individual behavioral characteristics of drivers, such as eyelid activity, nodding movements, eye closure, grip strength, etc.; ② Monitoring the physiological signals of drivers, such as electrocardiogram, electroencephalogram, muscle activity, etc.; ③ Monitoring vehicle parameters, speed, acceleration, etc. PERCLOS is a method that reflects the driver's fatigue by detecting the degree of closure of the driver's eyes, which can accurately reflect the fatigue state. Therefore, a non-contact, real-time driver fatigue detection system design based on ADSP-BF533 controller and PERCLOS method is proposed here. This system can accurately detect the driver's fatigue and give a warning.

2 System Overview
The system uses the fixed-point DSP processor BF533 of the high-performance architecture of the Blackfin series of ADI as the core processor. It has 2 MAC signal processing engines and uses an orthogonal RISC microprocessor instruction set. The unique dedicated video instructions give it significant video processing performance. The front end uses the CN00-303ROFD0 camera to collect the driver's facial image information in real time, and then transfers the data to the SDRAM in DMA mode through the PPI interface. After each frame of the image is transmitted, the BF533 processor analyzes the input data and video stream through the running fatigue detection program, detects the driver's fatigue status, and encodes the video MPEG-4 and saves it to the IDE hard disk. When the driver's fatigue is detected, a voice alarm can be issued through ISDl700. The overall structure diagram of the system design is shown in Figure 1:

3 System hardware design
The system hardware design mainly consists of four parts: video acquisition module, storage system, voice alarm module and power module. [page]

3.1 Video acquisition module
Video acquisition is a very important part of the system design. The resolution of the acquired image will directly affect the processing effect of the DSP. The CMOS image sensor uses PO3030K, which has a pixel array of 640×480 and has functions such as defect correction, edge enhancement, color correction, automatic white balance, automatic exposure control, and reflected light compensation. Its data output formats include: YCbCr4:2:2, YUV4:2:2, 5:6:5RGB, 5:5:5RGB and other modes, which can be controlled through the I2C bus. The interface connection diagram of the CMOS image sensor PO3030K and BF533 is shown in Figure 2.

The 12C_SCL and 12C_SDA pins of the CMOS image sensor are connected to PF0 and PF1 of BF533 respectively, and its pixel output ports D0~D7 are connected to PPI0~PPI7 of BF533. The pixel clock of PO3030K is used as the driving clock of PPI.
3.2 Memory system
The memory system includes program memory and data memory. The program memory is mainly used to store system programs, and the data memory is used for image cache and video storage. The program memory uses the electrically erasable and power-off protected Flash memory Am29LV800DB, which is 8 Mbit. The data width can be configured to 8 bits or 16 bits. The interface connection between Am29LV800DB and BF533 is shown in Figure 3.

In image processing, due to the large amount of image data and limited memory of BF533, the system externally expands SDRAM as a data buffer. SDRAM uses Hynix's HY57V561620C, which is a 4 Bankx4 Mx16Bit synchronous high-speed dynamic memory that fully meets the needs of data buffering. The interface connection between HY57V561620C and BF533 is shown in Figure 4.

The video data is stored in a large-capacity ATA_IDE hard disk. The ATA_IDE interface hard disk is the most commonly used storage device for computers. Its bus interface mode and control timing meet the bus control timing of the EBIU interface of BF533, and can be directly connected to the hard disk IDE interface through this interface. The connection interface block diagram is shown in Figure 5. The function of CPLD is to assign bus addresses to IDE hard disks. IDE hard disks have two address lines IDE_CS1 and IDE_CS2. IDE_CS1 selects the command block register, which contains registers for hard disk read and write control. These registers are configured to read and write hard disks; IDE_CS2 selects the control block register, which contains registers such as device control and status reading. Since the logic level of the hard disk is 5 V and the logic level of BF533 is 3.3 V, in order to match them, the bus driver 74LVC245 is used for level conversion. 74LVC245 is a bidirectional 8-bit bus driver, two of which are used for data bus driving and one for controlling the level matching of the signal line. The control pin DIR of 74LVC245 for data transmission direction has the same logic timing as the read control timing of BF533. It is connected to the AOE pin of BF533 to control the data transmission direction. IDE has two working modes in hardware connection: DMA transmission mode and PIO transmission mode. Since the DMA controller of BF533 only controls from the interface to the memory, it cannot perform DMA control on external devices. If you need to implement the DMA transmission mode of the hard disk, you must use a dedicated DMA control. In order to simplify the hardware design, the PIO16-bit mode is selected as the control mode of the hard disk.

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3.3 Voice alarm module
The voice alarm module uses Winbond's ISD1760. In addition to the advantages of ISD1400 series and ISD2500 series, such as anti-power-off, good sound quality, and easy use, the ISD1700 series also adds a humanized prompt function and precise operation of the storage address. It can record and play through the SPI interface. The interface is simple and compatible with the SPI interface of BF533 for easy control. ISD1760 has two working modes: independent key working mode and SPI mode. In the system, BF533 is connected to ISD1760 through the SPI interface. When the system detects driver fatigue, BF533 can send a playback command to LSD1700 through the SPI interface to issue a voice warning.
3.4 Power module
The design of the power module is an important guarantee for the normal operation of the entire system. Since the system design requires the use of the DSP internal analog phase-locked loop and considering that the system core operates at a frequency of 750 MHz, the DSP system is still powered by a linear power supply. Here we use TI's TPS76733 and National Semiconductor's LM1085. LM1085 is used to stabilize the external power input at 5 V and power 5 V devices, while TPS76733 is used to power 3.3 V devices. The power supply of the DSP core is adjusted by the voltage regulation circuit inside the DSP, and a stable core voltage of 0.8 to 1.2 V is generated through its own feedback loop. The TPS1100 with a very low start-up voltage drop is used as the core voltage adjustment tube. All power supply devices should be equipped with independent heat sinks, and when selecting the device package, a package with high output power should also be selected. The specific circuit design of the power supply circuit is shown in Figures 6 and 7.

4 System software design
The software design mainly completes the functions of video image acquisition, analysis and processing, compression storage and alarm. Its procedures mainly include: video data acquisition, algorithm processing and fatigue judgment of images, image compression storage, fatigue alarm, etc. The system software flow is shown in Figure 8. After the system is powered on, it will first self-check and then initialize the configuration. After the initialization is completed, the system will perform video acquisition, perform fatigue algorithm analysis on the acquired images to determine the driver's fatigue status, and compress and store the acquired video data. When the driver is detected to be in fatigue driving, the control will generate a voice alarm.

5 Conclusion
A solution based on BF533 driving fatigue detection is proposed, which adopts the most effective real-time PERCLOS driving fatigue evaluation solution. Experiments have proved that the system has the advantages of low power consumption, high reliability, good stability and low cost. The application of this system can reduce the occurrence of traffic accidents to a certain extent, reduce the harm caused by traffic accidents, and make drivers' driving and public travel safer.