Design and implementation of gate photon counter based on FSL bus

0 Introduction
Experiments in the field of optics, especially quantum optics, often require the detection of single coherent photons to collect experimental data. The commonly used configuration is a single photon detector plus a gate photon counter. The single photon detector at the front end is used to collect photon signals. Each detected photon generates a TTL pulse. The gate photon counter at the back end is used to record the number of TTL rising edges and communicate or synchronize with other devices such as PCs. The working mode of APD is relatively simple, while the gate photon counter requires different working modes due to different specific experimental requirements. It is difficult to have a universal counting mode that can meet the needs of various situations. Due to cost constraints, counters with fixed functions are often very expensive because there is no broad market. On the other hand, commercial counters purchased by industry and scientific research often cannot meet their specific needs, resulting in low work efficiency or even failure to meet the requirements.
The so-called gate photon counter is developed to meet the needs of single photon detection in single spin quantum control experimental research. Single spin quantum control is to control defects in crystals, such as quantum dots and diamond color centers. Its signal readout is generally achieved by detecting single photons generated by spins. There are three commonly used techniques in this type of experiment: gate photon counting, timing counting, and correlation function measurement. The system described in this paper establishes an expandable communication and control architecture that can add counting functions in different ways.

1 System structure design The
overall system structure diagram is shown in Figure 1. The Ethernet port of the PC is used to realize data communication and command transmission with the counting system. The PC sends commands such as working mode selection to the system through the network port, and the system sends data such as counting values ​​and counting status in different modes to the PC through the network port, and the PC processes the data. The main chip of the system uses Xilinx's SPARTAN 3E series XC3S500E. The photon counting input of the system is introduced by two BNC interfaces. These two interfaces can be configured by FPGA to make the photon counter work in different modes. The firmware of the system is burned in the FLASH chip. SDRAM provides a large-capacity storage space for loading Microblaze soft core code, counting application code, and storing counting data during operation.

The system uses FPGA as the processing center to implement various working modes. Its functional block diagram is shown in Figure 2. The functional modules mainly include the soft core Microblaze, the interface MPMC to the external memory, and the Counterpulse IP core that needs to be designed and implemented. The FSL bus is used to connect the Counterpulse IP core and the processor soft core to realize the configuration of the Counterpulse core by Microbalze and the data transmission from the Counterpulse core to Microblaze.

When the system is working, the Microblaze soft core receives commands sent by the PC through the network port, and selects and configures the working mode of the photon counting IP core through one FSL bus according to the commands. The counting IP core counts the external counting source, and the counting results and status data are sent to the Microblaze soft core through another FSL bus. The Microblaze soft core buffers the data in the DDRRAM and finally sends the data to the PC through the network port for analysis and processing.
The system has three working modes: Mode 1: Enable counting, when the enable signal is valid (high level is valid), the counting pulse signal input by the photon counting is counted; Mode 2: Fixed period counting, according to the set counting period, the counting pulse signal input by the photon counting is counted; Mode 3: Separate timing of start and stop signals, according to the input counting start signal and counting stop signal (both are valid on the rising edge), timing based on the system base frequency is performed to achieve function measurement.
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2 System design and implementation
2.1 System hardware block diagram
The hardware structure of the counting system is shown in Figure 3, which consists of FPGA, 64MB DDR memory, 16MB FLASH memory and 10M/100M Ethernet physical layer (PHY). When the system is working, the PC sends commands to the FPGA through the network port, the Microblaze soft core inside the FPGA configures the working mode of the counting IP core, and the FPGA counts the external counting source through two BNC interfaces, buffers the data in the DDRRAM, and finally sends the data to the PC through the network port.

2.2 Introduction to Main Components
2.2.1 Selection of FPGA Chip and Configuration Chip
The FPGA uses Xilinx's Spartan-3E series XC3S500E, which is produced using advanced 90nm manufacturing technology and has a device density of 500,000 gates. The Spartan3 series FPGA is developed by Xilinx specifically for electronic design with large capacity and low cost requirements, and can support multiple levels of I/O standards; it contains rich logic resources. XC3S500E has 360kbits of block RAM, 73kbits of distributed RAM, 10476 logic units, 20 18×18 multipliers and 4 DCM clock management modules.
The FPGA configuration chip is Xilinx's in-system programmable configuration chip XCF04S, which can provide an easy-to-use, low-cost and reprogrammable configuration data storage method for XC3S500E. The chip supports IEEE1149.1 standard JTAG boundary scan testing and programming. In this system design, XCF04S mainly stores the boot code for booting Microblaze soft core and application programs.
2.2.2 Storage chip
The RAM used in the system is Micron Technology's DDRSDRAM (MT46V32M16), which is a 16-bit bus width storage chip with a capacity of 512Mbit (32Mx16). It is used to load Microblaze soft core code and application code after power-on, and to buffer counting data. The FLASH chip is Intel StrataFlash parallel NORFlash, model 28F256J3, with a storage density of 256Mbit. It is used to save Microblaze soft core code and application code in this system.

3 Functional design and implementation
3.1 Application design and implementation of FPGA soft core Microblaze based on EDK
The system design tool mainly uses Xilinx's embedded development kit EDK, which is an integrated solution for designing embedded processing systems. It includes XPS for building hardware platforms and SDK for software configuration.
Microblaze is a 32-bit soft processor core launched by Xilinx, which supports the standard peripheral set of CoreConnect bus. The MicroBlaze processor runs at 150MHz clock and can provide 125 D-MIPS performance. This efficient soft core can be used in this system to implement processor functions, configure the counting IP core, and support Xilinx's clockgenerator, Ethernet and other IP cores. The system uses Verilog language to write the counting function as an IP core for the counter implementation, and hangs it on the Microblaze soft core through the FSL bus to implement the counting function.

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2 System Design and Implementation
2.1 System Hardware Block
Diagram The hardware structure of the counting system is shown in Figure 3, which consists of FPGA, 64MB DDR memory, 16MB FLASH memory and 10M/100M Ethernet physical layer (PHY). When the system is working, the PC sends commands to the FPGA through the network port, the Microblaze soft core inside the FPGA configures the working mode of the counting IP core, and the FPGA counts the external counting source through two BNC interfaces, buffers the data in the DDRRAM, and finally sends the data to the PC through the network port.

2.2 Introduction to Main Components
2.2.1 Selection of FPGA Chip and Configuration Chip
The FPGA uses Xilinx's Spartan-3E series XC3S500E, which is produced using advanced 90nm manufacturing technology and has a device density of 500,000 gates. The Spartan3 series FPGA is developed by Xilinx specifically for electronic design with large capacity and low cost requirements, and can support multiple levels of I/O standards; it contains rich logic resources. XC3S500E has 360kbits of block RAM, 73kbits of distributed RAM, 10476 logic units, 20 18×18 multipliers and 4 DCM clock management modules.
The FPGA configuration chip is Xilinx's in-system programmable configuration chip XCF04S, which can provide an easy-to-use, low-cost and reprogrammable configuration data storage method for XC3S500E. The chip supports IEEE1149.1 standard JTAG boundary scan testing and programming. In this system design, XCF04S mainly stores the boot code for booting Microblaze soft core and application programs.
2.2.2 Storage chip
The RAM used in the system is Micron Technology's DDRSDRAM (MT46V32M16), which is a 16-bit bus width storage chip with a capacity of 512Mbit (32Mx16). It is used to load Microblaze soft core code and application code after power-on, and to buffer counting data. The FLASH chip is Intel StrataFlash parallel NORFlash, model 28F256J3, with a storage density of 256Mbit. It is used to save Microblaze soft core code and application code in this system.

3 Functional design and implementation
3.1 Application design and implementation of FPGA soft core Microblaze based on EDK
The system design tool mainly uses Xilinx's embedded development kit EDK, which is an integrated solution for designing embedded processing systems. It includes XPS for building hardware platforms and SDK for software configuration.
Microblaze is a 32-bit soft processor core launched by Xilinx, which supports the standard peripheral set of CoreConnect bus. The MicroBlaze processor runs at 150MHz clock and can provide 125 D-MIPS performance. This efficient soft core can be used in this system to implement processor functions, configure the counting IP core, and support Xilinx's clockgenerator, Ethernet and other IP cores. The system uses Verilog language to write the counting function as an IP core for the counter implementation, and hangs it on the Microblaze soft core through the FSL bus to implement the counting function.

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Since the FSL bus is unidirectional, two FSL buses are used in the system to realize the bidirectional communication between Mieroblaze and the counting IP core. When facing the two FSL buses, the counting IP core plays the roles of MASTER and SLAVE. Therefore, the code of fsloprt.v should meet the read and write timing of the FSL bus interface at the same time. The read and write timing is shown in Figure 8 and Figure 9.

3.4 Connection between the Counting IP Core and the FSL Bus in EDK
In order to use the FSL bus, you should first configure Microblaze in the XPS graphical interface, and set the Number of FSL Links to 1 in Buses. Then add the FSL bus to the project twice in the IP Catalog.
After the counting IP core is written and passed the synthesis, import the IP core into the XPS project.
In XPS, connect the MFSL and SFSL of Microblaze and the counting IP core respectively, connect the MFSL end of Microblaze to the SFSL end of the counting IP core, and vice versa, connect the MFSL end of the counting IP core to the SFSL end of Microblaze. And configure the following in system.mhs:


Since the amount of data from the counting IP to Microblaze is large, the depth of the FSL bus is configured. For example, in the above code, PARAMETERC_FSL_DEPTH=128 is configured as 128 levels of depth.

4 Conclusion
In the design of the system, the photon counting IP core and the Mieroblaze soft core communicate through the FSL bus, and the FIFO buffer on the FSL bus is deeply expanded, which greatly enhances the transmission reliability of the light counting data. Since the system implements the three modes of gate photon counting in the form of IP core, compared with commercial counters on the market, the implementation method is flexible, easy to configure and expand. This method leaves a foundation for expansion of other potential counting needs of gate photons and has lower design and production costs.