MIPI-DSI Display Process D-PHY

• Video Streaming

• Pixel clock

• Display screen parameter analysis

• D-PHY Principle

• Link Basics

• Operation Mode

• I/O Signals

• DDR (Dual Data Rate) transmission method

Video Streaming

All modern computer monitors are raster displays, meaning that the displayed image is created by writing pixel by pixel, row by row, from left to right and from the top to the bottom of the monitor. The displayed image, or frame, consists of a rectangular array of pixels. A video stream consists of a series of frames displayed at a fixed time interval. This time interval can be described in Frames Per Second (FPS) or Hz. The roots of this process can be traced back to old cathode ray tube displays.

The working principle of LCD and OLED displays is derived from traditional CRT display technology, as shown above. They light up the image frame by frame by continuously scanning the back of the screen with an electron beam. The specific process is as follows:

The display of each frame of the image is completed by filling the pixels row by row from left to right and from top to bottom until the entire screen is completely filled. The electron beam first scans a row of images from left to right and emits light. After a row of scans is completed, the electron beam will turn off and return to the left side of the screen in a horizontal direction to prepare for the scanning of the next row of images. Then the electron beam will scan the entire screen row by row from top to bottom, and finally complete the display of a frame of the image.

After completing the display of one frame of image, the display system will continuously display multiple frames to generate a continuous and complete visual effect.

This line-by-line scanning working mechanism determines that the display system needs to introduce some synchronization signals and timing parameters to ensure the stable operation of the electron beam and thus obtain a good display effect.

The action of returning to the left side horizontally and returning to the first row mentioned here cannot be completed instantly, and it takes a certain amount of time to complete. Therefore, we introduce the following parameters to ensure a stable light beam to complete the display:

• HFP (Horizontal Front Porch) - The front porch of the horizontal sync signal, which represents the number of pixels that are not displayed after the valid pixel data ends. It is also the time interval required for the shutdown and beam rotation mentioned above.
• H-SYNC (Horizontal Sync) - Sent before the start of each line, the time it takes for the light beam to cross the screen horizontally.
• HBP (Horizontal Back Porch) - The back porch of the horizontal sync signal, which represents the inactive line after the horizontal sync signal, ensuring that the beam is stable when lighting the next line. After the HBP signal, the first valid display pixel starts to be sent.
• HACTIVE - Horizontal active pixels.

Switching between each frame also takes a certain amount of time. We introduce the following parameters to ensure a stable beam to complete the display:

• VFP (Vertical Front Porch) - The front porch of the vertical synchronization signal, which represents the invalid data line from the end of the data output of this frame to the beginning of the vertical synchronization cycle of the next frame, and is also the time required to turn the beam. After the VFP signal, the next frame begins to scan.
• V-SYNC (Vertical Sync) - Sent before each frame is displayed, it is the time interval required for the light beam to return vertically from the bottom of the screen to the top.
• VBP (Vertical Back Porch) - The back porch of the vertical sync signal, which represents the inactive line after the vertical sync signal. Similar to the previous HBP function, it is the time required to ensure the beam is stable. After the VBP signal, the first valid pixel line starts to be sent.
• VACTIVE - Vertically active pixels.

Pixel clock

The clock must keep the pixel data and synchronization signals in order. This clock is called the pixel clock. One pixel is transmitted per clock cycle. It is the main clock for most image display transmission systems. In the case of image sensors, the pixel clock time period sets the ADC conversion time interval for each pixel. It is the root clock for the HSYNC and VSYNC signals. The HSYNC signal indicates the start of each line, and the VSYNC signal indicates the start of each new frame.

The ENB signal is used to indicate active pixel data transmission. Without this signal, various pixel pipelines may mistake blanking data as pixel data with 0 value.

Display screen parameter analysis

The display parameters usually need to be included in the driver or DTB of the corresponding screen used by the customer. The following takes the RM67191 MIPI-DSI screen as an example:

#gpu/drm/panel/panel-raydium-rm67191.c
static const struct drm_display_mode default_mode = {
        .clock = 121000,
        .hdisplay = 1080,
        .hsync_start = 1080 + 20,
        .hsync_end = 1080 + 20 + 2,
        .htotal = 1080 + 20 + 2 + 34,
        .vdisplay = 1920,
        .vsync_start = 1920 + 10,
        .vsync_end = 1920 + 10 + 2,
        .vtotal = 1920 + 10 + 2 + 4,
        .width_mm = 68,
        .height_mm = 121,
        .flags = DRM_MODE_FLAG_NHSYNC |
                 DRM_MODE_FLAG_NVSYNC,
};

Screen parameters are sometimes provided as separate parameters. In the new version of BSP, they need to be provided through the above hsync_start, hsync_end and other parameters. The specific meaning and provision requirements of each parameter can be referred to the description in the DRM related driver:

/**
 * linux-imx/include/uapi/drm/drm_mode.h
 * struct drm_mode_modeinfo - Display mode information
 * @hdisplay: horizontal display size
 * @hsync_start: horizontal sync start
 * @hsync_end: horizontal sync end
 * @htotal: horizontal total size
 * @hskew: horizontal skew
 * @vdisplay: vertical display size
 * @vsync_start: vertical sync start
 * @vsync_end: vertical sync end
 */

From the above RM67191 and DRM driver, we get the following screen-related parameters of RM67191:

HFP = 20

H-SYNC = 2

HBP = 34

HACTIVE = 1080

VFP = 10

V-SYNC = 2

VBP = 4

VACTIVE = 1920

When actually integrating the display into your system, you need to follow these steps:

1. Obtain the various timing parameters mentioned above from the screen's datasheet and technical specifications, including horizontal and vertical blanking intervals, number of effective pixels, etc. These parameters are necessary to configure the screen driver.

2. In the driver of the display device, it is necessary to configure and initialize the relevant registers or variables according to the timing parameters obtained from the data sheet, such as setting the horizontal parameter values ​​of HFP, H-SYNC, HBP, HACTIVE, etc.

3. At the same time, these timing parameters also need to be configured and declared in the device tree (DTB) so that the operating system can correctly identify and drive the display device.

After completing the above driver and device tree configuration, the system can correctly initialize and light up the connected display screen.

In general, correctly obtaining the technical parameters of the display and accurately configuring them in the driver and device tree are the keys to successfully integrating the display device. Only in this way can the system stably output the expected image effect.

D-PHY Principle

As can be seen from the figure, the display process of the MIPI-DSI interface can be divided into two parts:

1. D-PHY: This is the source synchronous physical layer used by the CSI-2 and DSI protocols and is responsible for handling the physical and electrical aspects of communication.
2. Display Serial Interface (DSI): This is the interface between the processor and peripherals, which is based on the existing specifications of the MIPI Alliance.

This article will first introduce the working principle of D-PHY.

Link Basics

The MIPI specification uses a consistent set of terminology when discussing the components required to assemble a system based on CSI-2 or DSI.

• Line: The interconnection, wire, or lead between a single pin of a main processor and a pin of a peripheral device.
• Lane: Two lines are required to support differential signals. D-PHY uses differential pairs for high-speed data and clock transmission. This differential pair is called a Lane Interconnect, but is mostly referred to as a lane in technical documents.
• Link: A connection between two devices that includes a clock channel and at least one data channel. A link must include at least two PHYs and two channels of interconnection.

Operation Mode

There are four operating modes:

• Control mode
• High-Speed
• Escape
• Ultra Low Power State (ULPS) mode.

The data channel supports all four modes, but the clock channel supports only the control mode, high-speed transfer mode, and ultra-low power state modes. During normal operation, the data channel is in control mode or high-speed transfer mode. High-speed data transfer mode is used during data bursts, starting from the stop state (LP-11) of the control mode and ending in the stop state (LP-11) of the control mode. The channel is in high-speed mode only during data bursts. The following table describes the six physical states that the clock and data channels can enter.

In normal operation, the data channel is constantly switching between low-power control mode and high-speed data transmission mode.

I/O Signals

The D-PHY IO pins have two different electrical operation modes: single-ended mode and differential mode.

• The single-ended mode is called Low Power (LP) mode and is used for breakaway mode and control mode, system configuration/control between the host processor and peripherals. In LP mode, the IO circuit uses a traditional CMOS output buffer (with slope control) that switches between ground and VDD_IO. In LP mode, the two IO circuits that make up the channel can switch independently. They provide four different channel states: LP-00, LP-01, LP-10, and LP-11.
• The differential mode is called high-speed (HS) mode and is used only for data transmission. The differential mode has only two states: HS-0 and HS-1. In HS mode, the output polarities of the two IO circuits that make up the channel are always opposite and cannot be logic high or logic low at the same time. The figure below illustrates the difference in signal levels between HS and LP modes.

During normal operation, the data channel continuously switches between low-power control mode and high-speed data transmission mode.

DDR (Dual Data Rate) transmission method

• In a single data rate (SDR) synchronous data bus architecture (for example, SDRAM), data is sampled on either the rising or falling edge, but not on both. This means that the data rate is equal to the clock speed. Various low-power modes use a single data rate clock structure.
• The DDR (Double Data Rate) bus architecture can transfer data on every clock edge, not just on a single edge. Data transfer in HS mode uses the DDR transfer scheme. This means that for a given clock frequency (Fr), the data rate for each channel is 2 × Fr.

In the high-speed data transmission mode (HS) architecture, the data channel (Data Lane) generally adopts the dual data rate (DDR) transmission technology. The core of this technology is that the data sampling operation occurs not only on the rising edge of the clock signal (CLK Lane), but also synchronously on the falling edge, achieving two samplings in each clock cycle, thereby effectively doubling the data transmission efficiency. Specifically, whenever the state of CLK Lane changes from low to high (rising edge) or from high to low (falling edge), the data on the Data Lane is captured and transmitted.

Therefore, if the nominal frequency of the CLK signal is F Hz, then in DDR mode, the actual data transmission rate of each data channel (lane) reaches 2F bps (bits per second), achieving an effective doubling of the frequency. This feature is particularly important when evaluating and calculating the clock frequency of the Mobile Industry Processor Interface (MIPI), where DRPL (or Bit Clock) is a direct reflection of the data rate, and its value divided by 2 gives the equivalent frequency of the MIPI Clock, reflecting the conversion relationship between the system's internal processing clock signal and the data rate.

In summary, DDR transmission technology doubles the data transmission rate by sampling data on both the rising and falling edges of each clock cycle. This mechanism is widely used in high-speed data transmission systems, especially in the design and implementation of standard interfaces such as MIPI.