Chip First Talk: Revealing the Secrets of Wafer Manufacturing

Chips are one of the greatest inventions of our time. Without the advent of chips, it is difficult to imagine what the current electronic age would be like. It is precisely because of the invention of the chip that all functions can be condensed into a small chip.

A chip is the carrier of an integrated circuit, which is cut from a wafer and is usually an important part of a computer or other electronic device. Based on the wafer, the desired shape (i.e. various types of chips) can be completed by layer by layer. As the foundation of the semiconductor industry, the wafer is the basic carrier of the integrated circuit, so the wafer is not as important as It goes without saying. This article focuses on explaining the production and development status of wafers.

1.1. Early Years: The Birth of Semiconductor Wafers

The history of semiconductor wafers begins in the early 1960s, but its origins stretch back decades. The foundational work for semiconductors was laid in the 1930s and 1940s, when researchers like Julius Lillieneveld, John Bardeen, and Walter Bratan developed field-effect transistors (FETs) and point contacts The transistor, which marked the first step in solid-state electronics.

It was not until the early 1960s that the concept of semiconductor wafers truly took shape. Companies like Texas Instruments and Intel played a key role in the development and commercialization of wafers as an ideal substrate for manufacturing integrated circuits (ICs).

Silicon, an abundant element found in sand, has proven to be an ideal material for semiconductor wafers due to its semiconducting properties. The earliest wafers were relatively small, about 1 inch (2.54 centimeters) in diameter. However, as the demand for more complex and powerful electronic devices grows, the size of the wafers must also grow.

In the late 1960s and early 1970s, the industry transitioned from 1-inch wafers to larger sizes such as 2-inch (5.08 cm) and 3-inch (7.62 cm). This allows more components to be produced per wafer, increasing efficiency and lowering costs. By the late 1970s, 4-inch (10.16 cm) wafers became the industry standard.

1.2. Major leap: introduction of 6-inch wafers

The 1980s marked an important milestone in the history of semiconductor wafers with the introduction of 6-inch (15.24 cm) wafers. This leap enables manufacturers to further increase productivity and reduce costs, making semiconductors more suitable for a wider range of uses. With larger wafer sizes, the number of chips in a single batch increases exponentially, lowering the cost per chip.

The 6-inch wafer size dominated throughout the 1980s and 1990s. Continued growth in wafer size requires advancements in manufacturing processes and precision engineering to ensure wafers are uniform and defect-free.

1.3. Modern miracles: the era of 8-inch and 12-inch wafers

As the semiconductor industry continues to grow, the need for larger wafers becomes apparent. In the early 1990s, 8-inch (20.32 cm) wafers became the new standard, further reducing manufacturing costs and driving growth in consumer electronics, computers and telecommunications.

However, the desire for performance and miniaturization persisted, leading to the adoption of 12-inch (30.48 cm) wafers, also known as 300mm wafers, in the early 2000s. The transition from 12-inch wafers requires significant investment in manufacturing facilities and equipment, but the result is increased chip yield and lower cost per chip.

1.4. Future Prospects: The Journey Continues

Today, 12-inch wafers remain the industry standard, and ongoing research and development efforts are focused on larger wafer sizes. Although the transition from 450mm wafers (about 18 inches) faces significant technical and economic challenges, this prospect has been discussed.

Going further beyond size, the semiconductor industry is also exploring other materials, such as compound semiconductors and graphene, that could lead to new wafer types that offer improved performance for specialized applications.

1.5. Summary

The history of semiconductor wafers is a testimony to human wisdom and innovation. From their beginnings in the 1960s to the wonders of today's 12-inch wafers, these tiny chips of silicon have enabled the digital revolution and transformed the world of electronics. The diameter of the wafer usually has a variety of standard specifications, such as 200mm, 300mm, 450mm, etc., of which 300mm is currently the most commonly used specification. Larger wafer diameters allow more semiconductor devices to be produced from a single wafer, thereby increasing productivity and efficiency. If fabs were still producing 1-inch wafers today, they wouldn't be able to support the volume of smartphones, tablets, and PCs.

Wafer structure

2.1. Wafer

a. Definition: Wafer is the core raw material in the semiconductor manufacturing process. It is a round semiconductor substrate, usually made of single crystal silicon.

b. Status: The wafer is unprocessed raw material with no electronic circuits on it.

c. Purpose: Wafers are used to manufacture bare wafers, which are the starting point of the entire manufacturing process.

2.2. Die

d. Definition: A bare die is a single integrated circuit cut from a wafer, which contains a complete circuit design.

e. Status : The bare chip is not encapsulated and is a semi-finished product.

f. Purpose: The bare chip needs further testing and packaging to become the final chip.

2.3. Scribe Line

g. Definition: The scribe lines are edge lines without electronic circuits formed on the wafer. They are located on the edge of the wafer and are used to separate each chip on the wafer. The dies look like they are glued together, but there are actually gaps between them. This gap is called a scribe. The scribe line is the space where the diamond saw can safely cut the die.

h. Function: The scribing lines are the reference lines for cutting the bare chips on the wafer. They help to accurately separate individual chips during the subsequent wafer cutting process.

2.4. Flat area (Flat)

i.Definition: A flat area is a flat area on a wafer that helps identify the structure of the wafer and serves as a reference line during wafer processing.

j. Function: Since the structure of the wafer is too small to be seen by the naked eye, the flat area is used to determine the direction of the wafer.

2.5. Notch

k.定义： 凹槽是晶圆边缘的一种特殊设计，它比平面区域更为高效，因为它可以提供更多的参考点，帮助更准确地定位晶圆。带有凹槽的晶圆已经取代了平面区域。与带有平面区域的晶圆相比，带有凹槽的晶圆在生产更多的芯片方面更为高效。

l.作用： 凹槽的设计使得晶圆在生产过程中可以更高效地切割和定位，从而提高生产效率。

半导体晶圆的纯度、表面平整度、清洁度和杂质污染对芯片有着极其重要的影响，因此半导体晶圆的制造极为重要。晶圆生产制造是一个高度复杂且技术密集的过程，涉及多个步骤和精密的设备。随着技术的发展，晶圆生产制造的工艺也在不断进步，以支持更先进的制程和更高的制造质量。

3.1、原材料

沙子可以作为制造晶圆的原材料，主要原因在于沙子的主要成分是二氧化硅（SiO2），而硅（Si）是半导体的原料，二氧化硅也存在于普通沙子中，因此可以直接从沙子中提取,普通沙子只含有大约80%的二氧化硅。

3.2、晶圆加工

晶圆是由硅（Si）或砷化镓（GaAs）制成的单晶柱切割而成的圆形切片。为了提取高纯度的硅材料，需要硅砂，这是一种特殊材料，其硅含量高达95%，也是制造晶圆的主要原料。晶圆加工是制作和获得晶圆的过程。

3.2.1、收集沙子获取电子级硅

一旦沙子运抵制造厂，工厂人员会加入碳，并在炉中加热混合物。加热过程将碳与沙子的氧含量结合，产生二氧化碳并释放出99%的纯硅。搅拌机将硅分离出来，进一步提纯以生产适合生长晶体的电子级硅：

沙子（SiO2）在高温（2000摄氏度）下与碳反应，产生硅和二氧化碳（CO2）。这时，硅是冶金级的（MGS：Metallic Grade Silicon），即粗多晶硅。

在多晶硅净化后，纯净的三氯硅烷（TCS）在1100摄氏度下与氢气（H2）反应，生成电子级（EGS：Electric Grade Silicon）多晶硅和氯化氢（HCl），然后生产单晶硅。

3.2.2、晶体生长获取硅锭

电子级硅是多晶硅的性质。材料中每个晶体的接合点会干扰电子信号并使芯片出现缺陷。因此，在制造晶圆和芯片之前，制造商必须提取单个硅晶体。

有两种从电子级硅生产单晶硅的方法：

3.2.2.1、CZOCHRALSKI方法（直拉法）

CZOCHRALSKI方法在一个附有旋转坩埚的容器中熔化硅晶体。当有足够的熔融硅时，技术人员会向混合物中投入一个小锭。然后，熔融硅容器以与坩埚旋转相反的方向旋转，从而拉出硅棒，再将其切割成晶圆。

步骤一： 多晶硅和掺杂物的熔化

步骤二： 向熔融物中放入晶种

步骤三： 晶体开始生长

步骤四： 缓慢向上提拉棒，同时棒与下面的坩埚之间以反方向旋转

步骤五： 单晶硅生长完成

当前大部分的单晶硅是采用直拉法拉晶的。熔融硅的温度、流速、晶体和坩埚旋转速度的快慢，以及拉晶速度的准确控制对获得高质量的单晶硅锭起关键的作用。

3.2.2.2、浮区方法

浮区方法不使用石英坩埚，而是使用掺有氩气的原料。氩气使杂质硅晶体悬浮在空气中，杂质晶体穿过熔融区域与硅反应，形成单晶锭。然后将晶体拉回并提取。晶体上一个狭窄的区域熔融，此熔化区是沿晶体移动（在实践中，晶体被拉动穿过加热器）。熔化区将不纯固体在固体前边缘熔化并将更纯的物质凝固在后边留下。

区熔法对于如IGBT这类功率器件（高电阻率分立器件）的需求是理想的长晶方法。

生长过程还包括掺杂程序，它向硅中引入其他元素以操纵其导电性。

3.2.3、晶圆制造过程

生长过程产生的棒体，即硅棒或硅锭，得到硅棒后，按不同产品要求，使用电镀金刚石带锯或内圆切割刀片对其去头裁尾。内圆或外圆切割效率低、材料损失率大、加工质量低，故目前多采用金刚石带锯来切割硅棒。已切除圆角的硅棒表面并非规则的圆柱形，需使用电镀或烧结型金刚石杯形砂轮对硅棒滚圆，以达到所需直径。

从硅锭到单个晶圆的过程涉及几个关键步骤：

3.2.3.1、修剪/开槽

晶圆有一个凹口（6英寸的是平的），这个凹口应在锭完成时切割。这个凹口必须沿着特定的线切割。（添加晶向标记，对于大尺寸的晶圆，一般是柱面磨削出一道凹槽作为定位槽(Notch)，对于小尺寸的一般磨削出平边作为定位边(Flat)。）

3.2.3.2、将硅锭切割成晶圆

晶圆是使用带有嵌入式金刚石碎片的圆形刀片切割的。刀具旋转，但硅锭/锭只进行平移而不旋转。每个晶圆的厚度由两片刀片之间的距离决定。一般来说，晶圆的厚度为4英寸的525毫米，5英寸的625毫米，6英寸的675毫米，8英寸的725毫米，12英寸的775毫米，切割后，晶圆表面相对平坦且光滑，因此减少了后续研磨所需的时间和精力。然而，每次只能切割每把金刚石锯上的一个晶圆，这使得这种技术不如研磨（通过线锯切割）生产力高。切割分为内圆切割和线切割。这两种形式的切割方式被应用的原因是它们能将材料损失减少到最小，对硅片的损伤也最小，并且允许硅片的翘曲也是最小。

为了提高生产力，采用了多线切割方法，允许同时切割多个晶圆。一根高质量的钢线，长度可达100公里，直径在100到200微米之间，绕在一个旋转滚筒上，该滚筒具有数百个均匀间隔的凹槽。线锯的运行速度通常约为10米/秒，并涂有金刚石颗粒或用金刚石或碳化硅等磨粒的浆液润湿，以及载体流体（乙二醇或油）。

这种线锯方法的主要优点是能够用单根线同时切割数百个晶圆。然而，与使用圆锯切割的晶圆相比，切割后的晶圆表面更加凹凸不平，因此这些晶圆需要更长的后续研磨时间。

3.2.3.3、镭射标号

激光打标记的主要目的是为了在晶圆上标记各种信息，如制造商的标识、批次号、生产日期等，以便于追踪和质量控制。切割之后（切割是从单晶硅锭中切出圆形硅晶圆的步骤）晶圆可能还没有进行抛光，表面可能相对粗糙。在此时进行激光打标记可以确保标记不会被后续的抛光步骤所去除。这个步骤非常重要，因为它提供了晶圆的追踪信息，有助于质量控制和管理。

3.2.3.4、边缘缝合

切割良好的晶圆边缘有一个尖锐的圆柱边缘。需要将其磨成圆形以减少应力。在固定的槽中磨晶圆，就像磨刀一样。这主要是为了防止晶圆边缘开裂，并解决晶体格点中的任何不完美之处。

3.2.3.5、研磨

因为刚切割的晶圆表面一定有很多损伤和粗糙，这一步骤类似于化学机械抛光（CMP），可以使用研磨膏将其磨平改善硅片的总平坦度、翘曲度。因此，晶圆有时被称为抛光晶圆。通过研磨消除这些锯痕和切割过程造成的表面损伤是至关重要的，这一步骤旨在提高单晶硅的平坦度、曲率和平行度，确保其满足后续抛光过程的技术要求。

研磨时，硅片固定在如上图所示的上、下研磨盘(Lapping Plate)之间的载盘(Lapping Carrier)上，上下研磨盘相对方向旋转的时候，就能起到对硅片两面同时研磨的效果。

3.2.3.6、刻蚀

因为抛光仍然是机械过程，所以它仍然无法完全去除损伤，要将这些损伤去除，但尽可能低的引起附加的损伤。因此需要化学反应来去除表面缺陷。主要使用的化学品是硝酸（HNO3）+氢氟酸（HF）+醋酸（CH3COOH）的比例为4:1:3。在硝酸氧化过程中，氢氟酸会侵蚀二氧化硅（SiO2）。

3.2.3.7、抛光

在此之后，是湿化学机械抛光（CMP）过程，目的是在半导体晶圆的一侧实现高反射率的表面，且无划痕和损伤。化学蚀刻过程涉及使用由氢氟酸（HF）与硝酸和乙酸混合而成的溶液来溶解硅。在CMP过程中，晶圆被安装在夹具上并放置在CMP机器中，在那里它们经历结合了化学和机械抛光的过程。通常，CMP使用硬质聚氨酯抛光垫，并配有在碱性溶液中分散的细磨粒，如氧化铝或二氧化硅。CMP过程的最终产品是具有高反射率、“镜面”般表面的晶圆，在一侧没有划痕和损伤，适合制造半导体芯片。

3.2.3.8、清洗

在现代设备的生产中，晶圆清洗过程可能占整个制造过程的30%至40%，这突显了清洗半导体晶圆和处理底层表面的重要性。在进入晶圆制造过程之前，晶圆表面必须经过清洗，以消除任何附着的颗粒和有机/无机污染物。还必须去除硅氧化物。晶圆表面的污染物可能以离子和吸附元素、薄膜、松散颗粒、颗粒团簇和吸附气体的形式存在。在过去40年中，标准半导体晶圆清洗过程中使用的化学品基本保持不变。它依赖于使用氢氧化物和氨水溶液的RCA清洗程序，该溶液具有酸性特性。

3.2.3.9、测试

现在，既然已经拥有了完整的晶圆，晶圆的平整度和颗粒度是当今集成电路器件的关键影响因素，确保其最佳功能性和适用于操作要求是非常重要的。对晶圆完整性的两个主要威胁是电流和溶剂，因为这些都是导致损坏或断裂的主要原因。会不可避免的在其表面相应层中引入诸如：颗粒异物、划痕、缺失等缺陷，也有本身材质存在的缺陷。颗粒是可能引入的工序有刻蚀、抛光、清洗等。冗余物缺陷主要来自于生产加工中晶圆表面的灰尘、空气纯净度未到达标准以及加工过程中化学试剂等。为了减轻这些风险，因此，每一片晶圆的平整度(Flatness)和颗粒度(Particle)均需经过特定设计的仪器检查，以确保晶圆质量。如果符合标准，晶圆就被认为是准备好进行分发的。如果失败，晶圆将被标记并从批次中筛选出来。

检测原理： 颗粒异物在光刻时会遮挡光线，造成集成电路结构上的缺陷，污染物可能会附着在晶圆表面，造成图案的不完整。

通过以上工艺，晶圆（抛光片polished wafer）的制作就完成了。据了解，抛光片的使用约占硅片应用的70%，在抛光片的基础上，按照按照制程设计和产品差异衍生出退火片 (annealed wafer)及外延片(磊晶晶圆，epitaxial wafer)，其他特殊工艺包括 SOI（绝缘体上硅，Silicon-On-Insulator） 等。约占硅片应用的30%。

（1）抛光晶圆：

·应用场景： 主要用于数字与模拟集成电路、存储器、功率器件等芯片的制造。

·应用产品： 包括各种集成电路、存储器、功率器件等。

（2） 退火晶圆：

·应用场景： 用于消除晶圆表面的缺陷和应力，提高晶体质量，改善电学性能。

·应用产品： 广泛应用于半导体器件的制造，如晶体管和集成电路。

（3） 外延晶圆：

·应用场景： 用于在晶圆表面外延生长一层不同电阻率的单晶薄膜，以提高特定区域的电学性能。

·应用产品： 广泛应用于制造高频大功率器件、二极管、IGBT功率器件、低功耗数字与模拟集成电路及移动计算通讯芯片等。

（4） SOI晶圆：

·应用场景： 在衬底中间加入一层绝缘层，提供全介质隔离。

·应用产品： 广泛应用于数字SOI、RF-SOI、功率SOI、FD SOI、光学SOI等，应用于处理器芯片、连接SoC、射频应用、智能功率转换电路、智能手机、物联网、5G、汽车等领域。

这些晶圆类型在半导体制造中各自发挥着独特的作用，根据具体的应用需求和工艺条件选择使用。随着半导体技术的不断发展，这些晶圆类型的应用场景也在不断扩展和优化。

晶圆厂，即半导体制造工厂，也被称为晶圆代工工厂或晶圆制造厂，是生产集成电路（IC）和其他半导体产品的设施。

2024年，中美在芯片领域的竞争和争端进一步加剧。美国政府在3月30日发布了新的出口管制规定，针对半导体项目出口，特别是人工智能（AI）芯片和芯片制造工具。这些新规定旨在使中国更难获取美国的AI芯片和芯片制造设备。具体来说，新规定对向中国出口的芯片实施了更严格的限制，甚至适用于包含这些芯片的笔记本电脑。这一系列措施是美国对华半导体和AI芯片领域出口管制的再次升级。

这些新规定在2022年和2023年美国对华半导体出口限制的基础上进一步强化。例如，去年10月，美国商务部公布了针对中国的半导体出口管制最终规则，加严了对人工智能相关芯片和半导体制造设备的出口限制。美国政府的这些举措被指责为泛化国家安全概念、滥用出口管制措施，并实施单边霸凌行径，这些行为被认为严重违反了市场经济原则和国际贸易规则，对全球产业链和供应链稳定构成了威胁。

China has expressed strong dissatisfaction and firm opposition to these measures, emphasizing that the US actions have seriously undermined market rules and international economic and trade order. A spokesman for the Chinese Ministry of Foreign Affairs pointed out that what the United States has done seriously violated the principles of market economy and urged the United States to immediately correct its mistakes and stop imposing illegal unilateral sanctions and "long-arm jurisdiction" on Chinese companies. China has also been working hard to convey its desire to continue to maintain constructive relations with the United States, and emphasized that both sides should abide by economic and market rules, expand and deepen mutually beneficial business cooperation, and respect their respective rights to development.

These incidents reflect the increasingly fierce competition between China and the United States in the field of science and technology, especially in important fields such as semiconductors and AI technology. These U.S. moves could have a significant impact on the global semiconductor industry and could also affect U.S. companies that profit from selling products to the Chinese market. These restrictions could deprive companies like Nvidia of significant revenue streams, affecting market forecasts for semiconductor industry growth. At the same time, other countries without such strict restrictions may fill the gap in the Chinese market, thereby changing the global competitive landscape.

In 2024, the global wafer industry will show a significant growth trend, especially in China. According to a report by the International Semiconductor Industry Association (SEMI), global semiconductor production capacity is expected to grow by 6.4% in 2024, reaching the 30 million wafer mark per month. Among them, China's wafer production capacity growth is particularly significant, expected to increase by 13% to 8.6 million pieces per month, mainly due to the promotion of government and other incentives.

In the global foundry industry, mainland China's foundry market also shows a strong growth trend. From 2018 to 2022, the scale of mainland China's wafer foundry market will grow from 39.1 billion yuan to 77.1 billion yuan, with an average annual compound growth rate of 18.5%. This trend is expected to continue, and China's wafer foundry market will continue to maintain rapid growth.

TSMC (Taiwan, China), Samsung (South Korea), GlobalFoundries (USA), UMC (UMC - Taiwan, China), Semiconductor Manufacturing International Corporation (SMIC - Shanghai, China), Tower (Israel), Semiconductor Manufacturing Company (PSMC-Taiwan, China), HuaHong Group (Shanghai, China), World Advanced Technology (VIS-Taiwan, China), Hi-Tech (DB Hitek-South Korea)

In addition, the demand of the foundry industry is affected by the prosperity of the overall semiconductor industry. In 2022, the global wafer foundry market will be US$136 billion, an increase of 24% from 2021. By 2024, 15 new 12-inch wafer fabs are expected to come online, 13 of which are used to produce integrated circuits (ICs). These new wafer fabs are mainly used to produce power devices and advanced logic chips. Mainly work services.

Overall, the development trend of the wafer industry in 2024 shows that with the growth of global semiconductor production capacity and the expansion of the wafer foundry market, China's position in the wafer industry will be further strengthened. At the same time, the development of the foundry industry will also benefit from the overall growth of the semiconductor market and the support of government policies.

There are currently some differences in wafer technology at home and abroad, which are mainly reflected in the following aspects:

1. Technology maturity and advancement: Some leading companies in the world, such as TSMC and Intel, are leading the way in advanced process technologies (such as 7 nanometers, 5 nanometers and even smaller). Although domestic companies are catching up, there is still a gap between the most advanced process technology and the international leading level.

2. Production capacity and scale: Large international manufacturers usually have greater production capacity and scale and can support a wider product line and higher output. Although domestic companies are expanding rapidly, there is still room for improvement in overall production capacity and scale.

3. R&D investment and innovation capabilities: International manufacturers are usually stronger in R&D investment and innovation capabilities, and have more patents and technology accumulation. Although domestic companies are also increasing investment in R&D, they still need time to accumulate and make breakthroughs in some areas.

4. Supply chain and ecosystem: Major international manufacturers usually have more mature and complete supply chains and ecosystems, which helps them better respond to market changes and customer needs. Domestic enterprises are also developing rapidly in this area, but some aspects still need to be strengthened.

5. Policy and market environment: Domestic companies usually benefit from government support and market protection, which helps them develop rapidly in the domestic market. Major international manufacturers compete in the global market and face a more complex and changeable environment.

Generally speaking, although there are differences in wafer technology at home and abroad, domestic companies are rapidly catching up and constantly improving their technical strength and market competitiveness. With technological advancement and industry development, these differences are expected to gradually narrow.

The following are some well-known domestic fabs:

1. Semiconductor Manufacturing International Corporation (SMIC): It is the largest wafer foundry company in China and the fourth largest wafer foundry company in the world. Headquartered in mainland China, SMIC has made significant progress in multiple advanced process nodes. It is China's largest foundry company and provides a wide range of services from 0.35 micron to 14nm process nodes.

2. Hua Hong Semiconductor: Including Hua Hong NEC and Hua Hong Grace, it is another major wafer foundry company in China, focusing on a variety of process technologies. Focus on 12-inch wafer manufacturing and provide a variety of process nodes.

3. JCET: Mainly focused on packaging and testing business, but also has some wafer manufacturing capabilities.

4. Hefei High-Tech Integrated Circuit Co., Ltd.: Focuses on R&D and manufacturing of 12-inch wafer foundry services for 150nm to 90nm process nodes. Its products are widely used in many field.

5. CR Microelectronics: Provides wafer manufacturing services for a variety of process nodes.

6. Guangzhou Wafer: Focus on 12-inch wafer manufacturing and provide a variety of process nodes.

7. Wuhan XMC (XMC): focuses on the R&D and production of NAND flash memory and wafer-level packaging technology.

8. Tsinghua Unigroup: It owns a number of semiconductor-related companies, involving memory, wafer manufacturing and other fields.

9. Yangtze Memory Technologies Co., Ltd., YMTC: focuses on the R&D and manufacturing of 3D NAND flash memory technology.

10. Hefei Changxin Memory Storage Co., Ltd.: focuses on the R&D and production of DRAM memory.

11. Shanghai Huali Microelectronics (HLMC): Affiliated to Huahong Group, it focuses on the manufacturing of integrated circuits.

12. China Resources Microelectronics (CR Micro): Involves the R&D and production of various semiconductor products such as analog and mixed-signal integrated circuits, power devices, and sensors.

13. Silan Microelectronics: Focus on the manufacturing of analog and mixed-signal integrated circuits and discrete devices.

14. Guangzhou CanSemi Technology Co., Ltd.: focuses on the manufacturing of analog and mixed-signal integrated circuits.

15. Shenzhen Founder Microelectronics Co., Ltd.: Provides integrated circuit design and manufacturing services.

16. Zhuhai Allwinner Technology Co., Ltd.: focuses on the R&D and manufacturing of smart terminal chips.

17. Shenzhen BYD Microelectronics Co., Ltd.: Affiliated to BYD Group, it involves the R&D and production of power semiconductors, intelligent control ICs and other products.

These companies are important players in China's semiconductor industry, ranging from integrated circuit manufacturing to the R&D and production of specific semiconductor products. As China's status in the global semiconductor industry increases, the role and influence of these companies are also growing.

( Note: 12nm and 7nm in the process refer to the minimum distance or line width between transistors when manufacturing chips on a wafer. This size reflects the advancement of semiconductor manufacturing technology, that is, how small the transistors can be made. Process size Smaller, the transistors can be packed more closely, which means more transistors can be integrated on the same size wafer, thus improving performance and energy efficiency and reducing power consumption.)