How can we add isolation to an ADC without compromising its performance?

There are three aspects to consider when it comes to isolation:

• Ensure that the hot end has power from an isolated power source

• Isolate data to ensure data paths are isolated

• Clock isolation for the ADC (sampling clock or conversion signal) in case the hot side does not generate a clock

Flyback converters are widely used to isolate power supplies. Figure 1 shows the simplicity and feasibility of a flyback converter. The advantage of this topology is that it requires very few external components. A flyback converter has only one integrated switch. This switch can be a major noise source affecting the performance of the signal chain. For high-performance analog designs, a flyback converter introduces many breakpoints that cause electromagnetic radiation (known as EMI), which can limit the performance of the circuit.

Figure 1. Typical flyback converter topology.

Figure 2 shows the current in the transformer L1 and L2. In both the primary (L1) and secondary (L2) windings, the current jumps from a high value to zero in a short period of time. The current spikes can be seen in the I(L1)/I(L2) traces in Figure 3. Current and energy accumulate in the primary inductance and when the switch opens, they are transferred to the secondary inductance, generating transients. Transients caused by switching noise effects need to be reduced, therefore, snubbers and filters must be inserted in the design. In addition to the additional filters, another disadvantage of the flyback topology is the low utilization of magnetic materials while the required inductance is higher, resulting in a larger transformer. In addition, the hot loop of the flyback converter is also large and difficult to manage.

Another challenge with flyback converters involves the switching frequency variation. Figure 3 shows the frequency variation caused by a load change. As shown in Figure 3a, t1 < t2. This means that f _SWITCH changes as the load current decreases from a higher load current I1 to a lower load current I2. The change in frequency creates internal noise at unpredictable times. In addition, the frequency will also vary from device to device, making it more difficult to filter it because the filtering needs to be adjusted for each PCB. For a 20-bit SAR ADC with a 5 V input range, 1 LSB is equivalent to about 5 μV. The error introduced by EMI noise should be less than 5 μV, which means that the flyback topology should not be chosen when isolating the power supply for precision systems.

There are other isolated power architectures with lower radiated emissions. A push-pull converter is more suitable than a flyback converter in terms of emissions. A push-pull regulator like the LT3999 offers the possibility of synchronization with the ADC clock, which helps achieve high performance. Figure 4 shows the LT3999 in an isolated power circuit synchronized with the ADC sampling clock. Remember that the primary-to-secondary capacitor provides a return path for the switching noise to avoid the effects of common-mode noise. This capacitance can be implemented in the PCB design using overlapping top and second planes, as well as using actual capacitors.

Figure 2. The LT8301 switches current in a transformer winding.

Figure 3. (a) LT8301 frequency variation, (b) close-up of the frequency change from 2.13 ms to 2.23 ms.

Figure 4. LT3999 with ultralow noise post regulator.

Figure 5. LT3999 current waveform.

Figure 6. The LT3999 and its switching relationship to the SYNC pin.

Figure 5 shows the current waveforms at the transformer (primary and secondary currents), which makes better use of the transformer and provides better EMI behavior.

Figure 6 shows synchronization to an external clock signal. The end of the acquisition phase is aligned with the positive edge of the sync pin. Therefore, there will be a long quiet time of approximately 4μs. This allows the converter to sample the input signal within that time frame and minimize the effects of transients on the isolated power supply. The LTC2378-20 has an acquisition time of 312ns, which fits well within the <1μs quiet window.

Data isolation can be achieved using digital isolators, such as the ADuMx family of digital isolators. These digital isolators can be used for many standard interfaces such as SPI, I2C, CAN, etc. For example, the ADuM140 can be used for SPI isolation. To achieve data isolation, simply connect the SPI signals SPI Clock, SDO, SCK, and Busy to the data isolator. In data isolation, power is transferred from the primary side to the secondary side through the inductive isolation barrier. A current return path needs to be added, which is accomplished by a capacitor. This capacitor can be implemented in the PCB using overlapping planes.

Clock isolation is another important task. If a 20-bit high performance ADC with a 1 MHz sampling rate is used, such as the LTC2378-20, a signal-to-noise ratio (SNR) of 104 dB can be achieved. To achieve high performance, a jitter-free clock is required. Why shouldn’t a standard isolator like the ADuM14x family be used? Standard isolators add clock jitter, which limits the performance of the ADC.

Figure 7 shows the theoretical limits of SNR for different types of clock jitter at different frequencies. A high performance ADC like the LTC2378 has an aperture clock jitter of 4 ps, which gives a theoretical limit of 106 dB at a 200 kHz input.

Figure 7. Clock jitter versus ADC performance.

A more detailed block diagram of using a PLL to clean the clock is shown in Figure 11. You can use the ADF4360-9 as a clock cleaner and add a divide-by-2 on the output. The AD7760 is rated to support 1.1 MHz.

Figure 8. Clock isolation using standard isolators.

The standard clock isolator concept shown in Figure 8 includes:

• A good standard digital isolator like the ADuM250N has a jitter of 70 ps rms. For a 100 dB SNR target, the signal sampling rate is limited to 20 kHz due to clock jitter.

• Optimized clock isolators like the LTM2893 offer low jitter of 30 ps rms. For a 100 dB SNR target, the signal sampling rate is now 50 kHz, providing more bandwidth at full SNR performance.

Figure 9. Implementing clock isolation using an LVDS clock isolator.

• Figure 9: For higher input frequencies, LVDS isolators should be used. The ADN4654 provides 2.6 ps jitter, which is close to the best performance of the ADC. At 100 kHz input, the SNR limit due to clock jitter would be 110 dB.

Figure 10. Clock isolation using an additional PLL to clean up clock jitter.

• Figure 10: Using a PLL to clean up the clock. The ADF4360-9 can help reduce clock jitter.

Figure 11. ADF4360-9 used as a clock purifier.

Therefore, a 1 MSPS SAR ADC such as the LTC2378 cannot be directly supported. In this case, a low jitter trigger can help. It divides the clock by 2.

Figure 12. Flip-flops are used to step down the clock for use with the LTC2378.

Figure 13. Clock generation on the isolated (hot) side.

• Figure 13: Generating the clock locally is another option to obtain a clock with the required jitter performance. Local clock generation makes the clock architecture more complex because it introduces asynchronous clock domains into the system. For example, if two separate isolated ADCs are to be used, the absolute frequencies of the clocks will be different and sample rate conversion must be added to re-match the clocks. For some details on sample rate conversion, see Engineer-to-Engine Note EE-268.

Similar issues with clocking apply to high performance Sigma-Delta ADCs such as the AD7760. Here, the important clock signal is the jitter-free oversampling clock, for example 40 MHz. No additional divider is required in this case.

Isolated high-performance ADCs require careful isolation design and isolation technology selection to achieve high-performance SNR greater than 100 dB. Special attention should be paid to the isolated clock, as the effects of clock jitter can destroy performance. Secondary attention should be paid to the isolated power supply. Simple isolation topologies such as flyback can introduce high EMI transients.

For better performance, a push-pull converter should be used. Data isolation also needs to be considered (although less critical), and available standard components provide good performance with less impact on overall system performance. Introducing these three isolation topics will help designers come up with high-performance isolation system solutions.