Designing with VHDL

Engineers who want to effectively use VHDL for modeling, design, and synthesis of digital designs

• Basic knowledge of digital design

This comprehensive course provides a comprehensive introduction to the VHDL language. Emphasis is on writing reliable, synthesizable code, as well as enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This course is primarily targeted at Xilinx devices and FPGA devices. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course reinforces the understanding of key concepts by combining insightful lectures with labs. You will also learn best coding practices that will improve overall proficiency in VHDL and prepare you for advanced VHDL courses. Students with little or no knowledge of VHDL will be able to write efficient hardware designs and perform advanced HDL simulations after completing this course.

During this three-day course, you will gain invaluable hands-on experience.

The labs that accompany this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design process are covered in the labs. You can write, synthesize, simulate, and implement all the labs. The focus of the labs is on writing code to get reliable, high-performance circuits.

software tools

• Vivado Design or System Edition 2018.1
  

hardware

• Architecture: N/A*
  

• Demo Board: Kintex UltraScale FPGA KCU105 Development Board or Kintex-7 FPGA KC705 Development Board*

* This course does not focus on any particular architecture. For detailed instructions on the in-class experiment board or other customization information, please contact your local authorized training organization.

Skills acquired

After completing this comprehensive training, you will know how to:

• Implement the VHDL portion of the code for synthesis

• Identify the difference between behavioral and structural coding styles

• Distinguish between code for synthesis and code for simulation

• Use scalar and composite data types to express information

• Utilize parallel and sequential control structures to regulate information flow

• Implement common VHDL structures (finite state machines [FSM], RAM/ROM data structures)

• Simulate basic VHDL designs

• Writing VHDL testbenches and defining simulation-only structures

• Determine and implement optimal encoding methods

• Optimize VHDL code to target specific chip resources within Xilinx FPGAs

• Create and manage designs in the Vivado Design Suite environment

• training@e-elements.com

• training@v3best.com

For information on the course schedule, tuition and registration, please click "Read More"