Improving 48V power distribution performance

The power distribution network (PDN) is the backbone of any power system. As system power requirements continue to rise, traditional PDNs are under tremendous pressure to provide adequate performance. For power consumption and thermal management, there are two main ways to improve the impact of PDN on power system performance. One is to reduce PDN resistance by using larger cables, connectors, and thicker motherboard power planes. The other is to increase the PDN voltage to reduce current at a given transmission power, which allows the use of smaller cables, connectors, and thinner motherboard copper foil power planes, thereby reducing the corresponding size, cost, and weight.

For many years, engineers have used the first approach because it is compatible with the large ecosystem that has been built over decades for single-phase AC and 12V DC-DC converters and regulators. Other reasons include the inadequate performance of DC-DC converter topologies to efficiently convert higher voltages directly to the point-of-load (PoL) voltage, as well as the associated expense of these higher voltage converters and regulators.

However, modern power supply designs increasingly use the second approach, increasing the PDN voltage. The driving force behind this trend is the significant increase in system load power. Taking data centers as an example, the addition of artificial intelligence (AI), machine learning, and deep learning has rapidly doubled rack power to the 20kW range, while supercomputer server racks are approaching 100kW or more.

Figure 1: Ideal point-of-load power system. The regulator provides the highest efficiency when V _in = V _out . High current delivery is most efficient when it is closest to the point-of-load, minimizing I ² R losses.

This increase in power demand has prompted system engineers to reevaluate their entire PDN, from rack to rack distribution, all the way to the PDN on the server blades, as modern CPUs and AI processors consume more power. At the 5kW level in the rack, single-phase AC to the rack is normal. The AC is then converted to 12V and distributed to the server blades. At 5kW, the PDN current is 416A (5kW/12V), and the power distribution is done through a large number of cables.

Processor power has increased dramatically since about 2015, so rack power has increased to 12kW. Therefore, 1kA current must be managed within the rack of the 12V PDN. The OCP (Open Compute Project) Alliance, whose members mainly include cloud computing, server and CPU companies, will continue to develop its 12V rack design. The OCP rack moves from cables to busbars and distributes multiple single-phase AC to 12V converters within the rack to minimize the distance and impedance of the PDN from the rack to the server blades. The main difference from the previous rack power supply is that the single-phase AC power from the rack feed was a single phase of the three phases.

Companies that can build their own rack and data center solutions are beginning to move to 48V power distribution. This strategy reduces the high-current PDN problem to 250A for a 12kW rack, but introduces new challenges for power conversion in blade servers.

Figure 2: Transmitting high currents through the “last inch” creates a barrier for high-power processors. Vicor technology not only improves this performance, but also simplifies motherboard design.

When the rack power exceeds the 20kW range, the server rack PDN design will continue to evolve. In order to maintain the status quo of the original 12V system, people have to innovate in many aspects, but when the steady-state current of the processor introduced into the data center exceeds 1000 amperes and the peak current approaches 2000 amperes, it will make the traditional 12V PDN impractical. The core of AI is performance, and the 12V PDN will limit performance and competitiveness.

To address the challenges of high-power racks, the OCP Alliance is moving toward racks that can accommodate 48V PDNs. Moving from 12V to 48V power distribution reduces input current requirements by a factor of 4 (P=V×I) and cuts losses by a factor of 16 (power consumption = I ² R ). In addition, the automotive, 5G, LED lighting and display markets, as well as industrial applications, are also transitioning to 48V power distribution. As a result, the 48V power converter ecosystem is growing rapidly, and switching to 48V makes good business sense. But not all 48V converter topologies and architectures are the same. The 48V converter market has mixed performance, which is a reality that deserves careful consideration.

As high performance and power efficiency top the list of requirements for high-power racks and data centers, several companies are adopting three-phase AC to 48V for server blade power distribution. Alternatively, high-voltage DC (380V from rectified three-phase input) distributed within the rack can also be used. Several high-performance computing companies are using HVDC PDN for racks up to 100kW.

When the PDN powering the server blades is converted to 48V, the power conversion on the blades must also change. This shift has led to a variety of choices in architecture, topology and packaging for DC-DC converters and regulators.

The 48V model is relatively new to data center servers, but it is prevalent in communications applications such as routers and network switches because they use rechargeable 48V lead-acid battery backup systems. A common architecture previously used in data center servers is called intermediate bus architecture, or IBA. IBA includes an isolated unregulated bus converter that converts -48V to +12V, which is provided to a series of multiphase buck regulators for the load point. Some cloud computing and HPC companies initially replicated this architecture for their 48V systems, but as power increased and PoL voltages dropped below 1V, designers began to look for alternative architectures and topologies.

Power system architecture, switching topology, and packaging are very important for high-performance, high-density designs. As AI and CPU processor currents increase, the density of the power delivery circuit at the PoL becomes the most critical element in AI applications due to the PDN resistance between the regulator and the PoL.

The latest state-of-the-art AI processors have steady-state currents of around 1kA, with peak currents of 1.5kA to 2kA. Considering that the typical PDN resistance of a conventional multiphase buck regulator output for a processor is between 200 and 400µΩ, the resulting PCB power dissipation is steady-state (P = I ² R ) 200-400W, which is simply too high for any system to handle.

PDN losses have become the dominant factor in the efficiency and performance of DC-DC regulator designs. This is a point-of-load problem, and increasing the voltage is simply not practical (PoL voltages are dropping rapidly to maintain the validity of Moore's Law), so the only viable approach is to reduce the PDN resistance and place the regulator as close to the processor as possible. In the case of multi-phase buck regulators, 16-24 phases are usually occupied to support the high currents of AI processors. This is not a high current density solution and does not solve the PDN power consumption problem.

An alternative to IBA is Vicor’s Factorized Power Architecture (FPA), which consists of a pre-regulation stage (PRM) followed by a voltage transformation stage (VTM). This proprietary architecture optimizes the performance of each stage. The PRM performs non-isolated (48V is safety extra low voltage, SELV) regulation. Its 48V input is tightly regulated to provide a 48V output, and the required PoL voltage is converted in the VTM, which is a fixed ratio converter with an output voltage that is a fixed ratio of the input voltage.

Figure 3: MCM modules are capable of delivering high current and can be deployed in close proximity to the processor, either on the motherboard or on the processor substrate. This close proximity arrangement not only minimizes PDN losses, but also reduces the number of processor substrate BGA pins required for power.

This architecture and its performance are enhanced by the proprietary topologies used in the PRM and VTM. The PRM uses a zero voltage switching topology, while the VTM uses a proprietary resonant high frequency sine amplitude converter (SAC) topology. For conversion to the PoL voltage, zero voltage and zero current switching . The VTM is actually a DC-DC transformer, where the voltage is reduced by a ratio of 1/K and the current is increased by a factor of K. The VTM, also called a current multiplier, is a high current density PoL converter. (New products currently reach 2A/ mm2 .) It can ^be placed next to the processor because it uses innovative ChiP packaging technology and supports high-density integrated magnetic components.

This level of high current density provides designers with great flexibility. Engineers can choose between lateral or vertical power delivery (LPD and VPD), depending on the processor current. In LPD, the current multiplier is placed within a few millimeters of the AI ​​processor, either on the same substrate or directly on the motherboard, reducing the PDN resistance to approximately 50µΩ.

Figure 4: Vertical Power Delivery (VPD) further eliminates power distribution losses and VR PCB real estate. VPD is similar to the Vicor LPD solution, with the addition of the integration of bypass capacitors in the current multiplier or GCM module.

To further improve performance, VPD moves the current multiplier to just below the processor, where its output power pin map closely matches the spacing and location of the processor power pins above it. In addition, the current multiplier package also integrates high-frequency bulk capacitors, which are generally located just below the processor on the motherboard or substrate. This current multiplier is called a geared current multiplier (GCM). VPD can reduce the PDN resistance to an incredible 5 to 7µΩ, helping AI processors achieve their true performance.

With such a complex power problem, a holistic design approach ensures successful high-performance results. Innovations in architecture, topology, and packaging are needed to solve the toughest power challenges. Increasing the voltage of the PDN can solve a wide range of system performance challenges. Reducing PDN resistance is key to unlocking the next generation of HPC power and delivering on the promise of AI.